Optimization and Representation of Non-Slicing VLSI Floorplanning

The recent advances in the semiconductor nano technologies increase the complexity of very large-scale integration circuits. With the fabrication technology entering the deep Nanoscale era more demand at greater huge complication of integrated chip design arises. The development of eccentric floor p...

Full description

Saved in:
Bibliographic Details
Published in2023 4th International Conference on Smart Electronics and Communication (ICOSEC) pp. 26 - 31
Main Authors Jeyarohini, R., Britto, K. R. Aravind, Ramkumar, M. P.
Format Conference Proceeding
LanguageEnglish
Published IEEE 20.09.2023
Subjects
Online AccessGet full text

Cover

Loading…