Optimization and Representation of Non-Slicing VLSI Floorplanning

The recent advances in the semiconductor nano technologies increase the complexity of very large-scale integration circuits. With the fabrication technology entering the deep Nanoscale era more demand at greater huge complication of integrated chip design arises. The development of eccentric floor p...

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Bibliographic Details
Published in2023 4th International Conference on Smart Electronics and Communication (ICOSEC) pp. 26 - 31
Main Authors Jeyarohini, R., Britto, K. R. Aravind, Ramkumar, M. P.
Format Conference Proceeding
LanguageEnglish
Published IEEE 20.09.2023
Subjects
Floor Planning
Layout
Metaheuristic algorithm
Minimization
Particle Swarm Optimization
Shape
Simulated annealing
Very Large-Scale Integration
White space area
White spaces
Wire length
Wires
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Summary:The recent advances in the semiconductor nano technologies increase the complexity of very large-scale integration circuits. With the fabrication technology entering the deep Nanoscale era more demand at greater huge complication of integrated chip design arises. The development of eccentric floor plan without over-lapping is the intention of VLSI floor planning. The major objective of VLSI is concerned with floor plan area minimization and wire length optimization. Floor planning is the important step that creates an optimal layout solution for the VLSI circuits. This article attempted to collect the necessary information in reducing the floor plan layout by means of reducing the wire length, white space area with the employment of computer aided metaheuristic algorithms. In order to ease the process of execution the best local search algorithms like a Particle Swarm Optimization and Simulated Annealing algorithms is compared.
DOI:10.1109/ICOSEC58147.2023.10276362