Simulation and Synthesis of Current Mode Logic and Reversible Logic Based Arithmetic Circuits

• Published in: 2023 International Conference on Intelligent Systems for Communication, IoT and Security (ICISCoIS) pp. 133 - 138
• Main Authors: Ramesh, J., Madhumitha, K., Soundaryalaxmi, B., Rao, Deepak Appa, Kanisha, R.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 09.02.2023
• Subjects: CMOS technology; Integrated circuit modeling; Logic gates; MOS Current Mode Logic; Power; Power demand; Power dissipation; Reversible Logic; Security; Semiconductor device modeling; Static CMOS Logic
• DOI: 10.1109/ICISCoIS56541.2023.10100442

Due to the escalating need for compact and portable electronics, component shrinking is steadily advancing. Each logical procedure and component tend to lose energy as heat while being used. Reversible logic and current mode logic can be used to reduce power dissipation caused by the irreversible logic used in current systems. Reversible logic gates are n-input, n-output devices that allow for the recovery of all inputs from the output, resulting in reduced power usage. Current Mode Logic (CML) uses less current from the power source and has a more reliable switching current than CMOS. Reversible logic is initially used in higher levels of abstraction to implement various adders, multipliers, and delay units. Based on the power consumption analyzed using logic-level power analysis, the two least power-consuming adders and multipliers are chosen for implementation in circuit-level simulation. The proposed reversible logic methodology is more power-efficient, affordable, and has a simpler design than those already in use.