Soc Design of Intelligent Recognition Based on RISC-V - Ge, Zhilai; Xiao, Penghao; Li, Mengxue; Wang, Haipeng (2022 International Conference on Automation, Robotics and Computer Engineering (ICARCE), 2022)
The RISC-V open source instruction set architecture has received extensive attention in the field of embedded low power consumption due to its advantages such as simplicity and low power consumption. However, due to the low computational power provided by RISC-V, it is difficult to deploy convolutional neural networks with high algorithm complexity. If deep learning cannot be applied to RISC-V, it will limit the promotion of RISC-V in the fields of automatic driving, face recognition, target tracking, natural language processing, etc. In this design, a CNN accelerator is designed, which is connected to the co-processor interface of RISC-V, and a set of user-defined instruction sets is designed to call the CNN accelerator to solve the problem that RISC-V cannot deploy neural networks. Through testing, when the soc system power consumption is only 0.4w, the co-CNN accelerator can accelerate the CNN more than 1000 times, meeting the requirements of low-power embedded field.