Design and Implementation of Low-Power and Area-Efficient Flip Flop with Redundant Pre-Charge Free Operation

• Published in: 2023 4th International Conference on Smart Electronics and Communication (ICOSEC) pp. 201 - 209
• Main Authors: Vishal, R., Vidyanidhi, P. Sri, Deepak, R., Agrawal, Sonali
• Format: Conference Proceeding
• Language: English
• Published: IEEE 20.09.2023
• Subjects: Delays; Digital systems; Dynamic; Flip-flop; Low-power; Power demand; Precharge-free; Static; Time-frequency analysis; Transistors; True single-phased clocking (TSPC); Voltage; Voltage control

As basic components, optimizing the power consumption of flip-flops (FFs) can significantly reduce the power of digital systems. This study proposes a static flip-flop architecture that is designed with 22 transistors using a single-phased clocking scheme and has a precharge-free operation. This arc...