A 13 × W, 94 mK Resolution, CMOS PD ΔΣ M Temperature-to-Digital Converter With Power-Gating Technique

This paper presents a CMOS phase-domain delta-sigma modulator (\mathrm{P}\mathrm{D}\Delta\Sigma \mathrm{M}) that digitizes temperaturedependent phase shifts resulting from driving a poly-phase filter (PPF) at a constant frequency. Closed-loop architecture with a power-gating technique is applied to...

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Bibliographic Details
Published inESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC) pp. 17 - 20
Main Authors Huang, Ying-Jie, Huang, Yu-Chiao, Chiu, Yu-Hao, Tsai, Wen-Pin, Liao, Yu-Te
Format Conference Proceeding
LanguageEnglish
Published IEEE 11.09.2023
Subjects
CMOS
delta-sigma modulator
Europe
Frequency modulation
Linearity
phase domain
Power demand
Solid state circuit design
Temperature distribution
temperature sensor
Temperature sensors
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Summary:This paper presents a CMOS phase-domain delta-sigma modulator (\mathrm{P}\mathrm{D}\Delta\Sigma \mathrm{M}) that digitizes temperaturedependent phase shifts resulting from driving a poly-phase filter (PPF) at a constant frequency. Closed-loop architecture with a power-gating technique is applied to improve linearity and power efficiency. The design is implemented in a 0.18\mu \mathrm{m} CMOS process. The temperature sensor has an inaccuracy of ± 2.2°C(3σ) from -40°C to 85\circ \mathrm{C}. Furthermore, the design achieves a resolution of 94 mK at 1 \mathrm{k}\mathrm{S}\mathrm{a}/\mathrm{s}, while the chip area is 0.19 \mathrm{m}\mathrm{m}^{2}. The power consumption is 13 \mu \mathrm{W}, resulting in an inaccuracy FoM of 161.1 \mathrm{n}\mathrm{J}\cdot\%^{2}.
ISSN:2643-1319
DOI:10.1109/ESSCIRC59616.2023.10268694