Ultimate MRAM Scaling: Design Exploration of High-Density, High-Performance and Energy-Efficient VGSOT for Last Level Cache

• Published in: Technical digest - International Electron Devices Meeting pp. 1 - 4
• Main Authors: Gupta, M., Xiang, Y., Garcia-Redondo, F., Cai, K., Abdi, D., Liu, H.-H., Rao, S., Hiblot, G., Couet, S., Garcia-Bardon, M., Hellings, G.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 09.12.2023
• Subjects: Delays; Integrated circuit interconnections; Magnetic resonance imaging; Magnetic tunneling; Metals; Random access memory; Resistance; Switches; Voltage; Writing
• ISSN: 2156-017X
• DOI: 10.1109/IEDM45741.2023.10413886

The Voltage-Gated Spin-Orbit-Torque (VGSOT) MRAM is a unique multi-bit SOT-MRAM implementation with the aid of voltage-controlled magnetic anisotropy (VCMA). In this paper, we explore the Power-PerformanceArea scaling potential of VGSOT for last-level cache (LLC) towards 14-Å node, and profile the required device design space based on a hardware-validated compact model. We highlight the outstanding bit density of VGSOT-4MTJ up to ~ 3× of iso-node SRAM, which in an LLC-relevant, (16 - 32) MB memory macro brings down the global interconnect length by 40 %; this in turn translates to max. 60 % and 30 % overall delay and energy reduction, respectively, over SRAM. We nonetheless emphasize the essential all-aspect technology co-optimization of SOT track (in resistivity and Spin Hall angle) and MTJ stack (in VCMA efficiency) for unlocking the desired selective writing in a multi-bit VGSOT cell. We conclude that the multi-bit VGSOT provides an alternative, density-enabled, interconnect-centric scaling route for LLC.