Research on control flow conversion technique based on Domestic Sunway compiler

• Published in: 2022 7th International Conference on Intelligent Computing and Signal Processing (ICSP) pp. 1340 - 1344
• Main Authors: Kong, JinYing, Han, Lin, Xu, JinLong, Nie, Kai
• Format: Conference Proceeding
• Language: English
• Published: IEEE 15.04.2022
• Subjects: Costs; if-conversion; Instruction level parallelism; Parallel processing; Pipelines; Process control; Scientific computing; Signal processing; Signal processing algorithms; Sunway compiler; Sunway processor
• DOI: 10.1109/ICSP54964.2022.9778356

Control flow conversion replaces a series of control-dependent instructions with only data-dependent instructions. Sunway compiler uses this technology to eliminate pipeline pauses caused by conditional branch statements, thereby improving the instruction-level parallelism of the overall program. Based on the instruction set characteristics and structural characteristics of the Sunway processor, the improvement is made for the inaccurate calculation of the control flow conversion cost in the RTL stage in the Sunway compiler. In the control flow conversion benefit judgment algorithm, by adding control flow basic blocks The execution frequency of the branch statement is weighted to calculate the expected value of the execution cost of the basic block of the branch statement to improve the accuracy of the cost calculation during the conversion process. Using SPEC2006 Benchmarks to test the performance of the improved compiler on the new generation of Sunway 1621 server, the overall performance is increased by 2%, and the maximum performance of a single subject is increased by 6%. This work improves the control flow conversion in the Sunway compiler. Efficiency is of great significance in order to give full play to the performance advantages of the domestic Sunway processor architecture.