Implementing fair queueing in ATM switches: the discrete-rate approach

• Published in: Annual Joint Conference of the IEEE Computer and Communications Societies Vol. 1; pp. 272 - 281 vol.1
• Main Authors: Chiussi, F.M., Francini, A.
• Format: Conference Proceeding Journal Article
• Language: English
• Published: IEEE 1998
• Subjects: Asynchronous transfer mode; Calendars; Costs; Degradation; Delay; Global Positioning System; Processor scheduling; Scheduling algorithm; Sorting; Switches

The total implementation cost of schedulers which approximate the generalized processor sharing (GPS) policy is dominated by the complexity of maintaining and sorting the time-stamps for all connections. Several approaches have been proposed which reduce the cost of the sorting operation and only in...