Real-time Implementation of Delay Efficient DCT Based Hearing Aid Algorithm Using TMS320C5505 DSP Processor

• Published in: 2021 Innovations in Power and Advanced Computing Technologies (i-PACT) pp. 1 - 8
• Main Authors: Swamy, K. Ayyappa, Alex, Zachariah C., Ramachandran, Prakash, Mathew, T. Lazar, Sushma, C., Padmaja, N.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 27.11.2021
• Subjects: Auditory system; Computers; Discrete Cosine Transform; DSP processor; filter bank; Filter banks; hearing aid; Hearing aids; Real-time systems; sensorineural hearing loss; Simulation; Technological innovation
• DOI: 10.1109/i-PACT52855.2021.9696632

In the case of sensorineural hearing loss, the hearing aid needs to amplify the audio signal selectively based and frequency and very sensitively based on the hearing threshold. In this paper, we proposed to implement a new 16-point Discrete Cosine Transform (DCT) base delay efficient algorithm for hearing aid applications. This proposed algorithm gives better matching error with smaller delay due to uniform resampling and recursive modification of hearing thresholds in an audiogram. Delay and matching error are the main parameters in analysing the performance of the hearing aid algorithm. Four audiograms with various degrees of hearing loss are used to test the suggested method. When compared to filter bank approaches, the suggested algorithm has a lower matching error and a faster response time. The proposed algorithm is implemented on a TMS320C5505 DSP processor to validate the simulation results.