Implementation and Physical Design of 8/4-Bit Signed Divider

• Published in: 2021 8th International Conference on Signal Processing and Integrated Networks (SPIN) pp. 829 - 834
• Main Authors: Purohit, Shubham, Laddha, Prashant, Parekh, Rutu
• Format: Conference Proceeding
• Language: English
• Published: IEEE 26.08.2021
• Subjects: Bandwidth; Delays; Non-Restoring; Physical design; Power demand; Registers; Signal processing; Signal processing algorithms; Signed divider
• DOI: 10.1109/SPIN52536.2021.9566020

This paper focuses on implementing a signed binary divider using Verilog and performing a physical design process i.e. register transfer level (RTL) to graphic design system-II (GDSII) on 180nm and 45nm technology nodes to analyze different parameters such as delay, area, power, and bandwidth. It also extends the unsigned divider to the signed divider and hence increases the range of division. On 180nm, this divider consumes 14263.2 μm 2 area, the power consumption of 20 μW and bandwidth of 666.66 Mhz, whereas for 45nm node area consumption of this divider is 600.130 μm 2 with a power consumption of 17.88 μW and bandwidth of 892Mhz.