Machine Learning Techniques for the Energy and Performance Improvement in Network-on-Chip (NoC)

On resource-constrained embedded devices (e.g., Internet of Things nodes), deep neural network inference requires specialized architectural solutions to deliver the greatest possible performance, energy, and cost trade-offs. In this regard, a Network-on-Chip architecture with many parallel and speci...

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Bibliographic Details
Published in2021 4th International Conference on Computing and Communications Technologies (ICCCT) pp. 590 - 595
Main Authors RamaDevi, J, Pathur Nisha, S, Karunakaran, S, Hemavathi, S, Majji, Sankararao, Shunmugam, Anandaraj
Format Conference Proceeding
LanguageEnglish
Published IEEE 16.12.2021
Subjects
Correlation
Deep learning
Energy consumption
Machine Learning
Machine learning algorithms
Memory management
Network-on-Chip
neural network
Neural networks
Performance evaluation
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DOI10.1109/ICCCT53315.2021.9711872

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Summary:On resource-constrained embedded devices (e.g., Internet of Things nodes), deep neural network inference requires specialized architectural solutions to deliver the greatest possible performance, energy, and cost trade-offs. In this regard, a Network-on-Chip architecture with many parallel and specialized cores is one of the most promising (NoC). An architecture parameter that impacts deep neural networks' performance is the number and size of memory interfaces. Using these and other architectural criteria, we investigate the design space that can be created. We demonstrate how on-chip communication dominates delay while memory consumes the majority of energy. According to the findings, a new research area devoted to improving the performance and energy efficiency of on-chip communication fabrics and memory subsystems should be estavlished.
DOI:10.1109/ICCCT53315.2021.9711872