Power Efficient Approximate Divider Architecture for Error Resilient Applications

• Published in: 2022 IEEE 6th Conference on Information and Communication Technology (CICT) pp. 1 - 6
• Main Authors: Shriram, Abhay, Tiwari, Ayush, Anil Kumar, U., Ravi Teja Karri, Babu, Veeramachaneni, Sreehari, Ershad Ahmed, Syed
• Format: Conference Proceeding
• Language: English
• Published: IEEE 18.11.2022
• Subjects: Approximate computing; Approximate divider; Complexity theory; Computer architecture; Design methodology; Hardware; Image processing; Information and communication technology; Power demand
• DOI: 10.1109/CICT56698.2022.9997960

Approximate computing is an emerging paradigm in error-tolerant applications that leads to power-efficient designs without significant loss in quality. The divider in these applications have complex hardware and more latency among the computational blocks resulting in power consumption. Hence approximating the division module would lead to designs with vastly improved power efficiency. A new approximate subtractor (AxSUB) is proposed in this paper with the intent to reduce the hardware complexity while achieving accuracy within permissible limits. The proposed AxSUB and existing approximate subtractor units are used in the restoring array division (RAD) architecture to prove the efficacy of the AxSUB. Comprehensive error and synthesis analysis are performed on RAD architectures implemented using AxSUB, and existing methods. Our proposed design achieved a 21% decrease in area and a 28% decrease in power consumption compared to the exact design. The proposed and existing RAD architectures is implemented on change detection applications to validate the quality-effort tradeoff.