Embedded PLL Phase Noise Measurement Based on a PFD/CP MASH 1-1-1 ΔΣ Time-to-Digital Converter in 7nm CMOS

• Published in: 2020 IEEE Symposium on VLSI Circuits pp. 1 - 2
• Main Authors: Chou, Mao-Hsuan, Chang, Ya-Tin, Tsai, Tsung-Hsien, Lu, Tsung-Che, Liao, Chia-Chun, Kuo, Hung-Yi, Sheen, Ruey-Bin, Chang, Chih-Hsien, Hsieh, Kenny C. H., Loke, Alvin L. S., Chen, Mark
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.06.2020
• Subjects: Built-in self-test; Delays; Jitter; Noise measurement; Phase locked loops; Phase measurement; Phase noise
• DOI: 10.1109/VLSICircuits18222.2020.9162789

We propose an embedded PLL phase noise measurement macro for cost-effective SoC test based on a phase-frequency detector/charge pump (PFD/CP) MASH 1-1-1 ΔΣ time-to-digital converter (TDC). The decimated TDC output stream is post-processed to extract the phase jitter and noise spectrum. Measuring low jitter requires a short and precise reference delay which we generate with a charge-based pseudo-DLL that locks to the reference delay itself. Using a 14GHz LC-PLL built in 7nm CMOS as a demonstration vehicle, this macro measures 2.80ps rms jitter which closely matches 2.89ps measured by a phase noise analyzer. The built-in self-test (BIST) macro consumes 12.2mW on a 1.2V supply, occupying only 0.066mm 2 which is only one-third of the PLL area.