5nm Low Power SRAM Featuring Dual-Rail Architecture with Voltage-Tracking Assist Circuit for 5G mobile application

Voltage Auto Tracking Cell Power Lowering (VACPL) Write Assist circuit is proposed for low-power SRAM with dual-rail architecture. VACPL adaptively controls the cell voltage with respect to the dual rail offset voltage to maximize bitcell write-ability. A 5nm EUV FinFET test chip demonstrates 210mV...

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Bibliographic Details
Published in2021 Symposium on VLSI Circuits pp. 1 - 2
Main Authors Baeck, Sangyeop, Lee, Inhak, Tang, Hoyoung, Seo, Dongwook, Choi, Jaeseung, Song, Taejoong, Kye, Jongwook
Format Conference Proceeding
LanguageEnglish
Published JSAP 13.06.2021
Subjects
5G mobile communication
Access Disturb Margin
Cell Power Lowering
Computer architecture
Dual rail SRAM
FinFETs
Microprocessors
Rails
Random access memory
Very large scale integration
Voltage-Tracking Assist
Write Margin
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Summary:Voltage Auto Tracking Cell Power Lowering (VACPL) Write Assist circuit is proposed for low-power SRAM with dual-rail architecture. VACPL adaptively controls the cell voltage with respect to the dual rail offset voltage to maximize bitcell write-ability. A 5nm EUV FinFET test chip demonstrates 210mV VMIN improvement and 4.7x larger range of operating voltage with VACPL. The proposed VACPL and VATA achieves 95.2% leakage power reduction by lowering VDDC by 400mV in 5nm 5G mobile device.
ISSN:2158-5636
DOI:10.23919/VLSICircuits52068.2021.9492368