Power and Area Efficient Router with Automated Clock Gating for Neuromorphic Computing

• Published in: 2019 32nd IEEE International System-on-Chip Conference (SOCC) pp. 27 - 32
• Main Authors: Pu, Junran, Nambiar, Vishnu P, Mani, Aarthy, Goh, Wang Ling, Do, Anh Tuan
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.09.2019
• Subjects: asynchronous router; clock gating; network-on-chip; neuromorphic computing
• ISSN: 2164-1706
• DOI: 10.1109/SOCC46988.2019.1570548462

Network-on-Chip has been widely used as an interconnection fabric due to its high scalability. However, traditional router designs target multiprocessor systems-on-chips, and therefore needs to be improved according to the characteristics of neuromorphic computing. This paper proposes an ultra low power and low area router for neuromorphic computing. Clock gating technique is used to reduce router power consumption by reducing clock activities. The proposed router uses small FIFO based interface links to reduce router area. A modified round robin arbiter is proposed to reduce the router latency. The wormhole model is improved to make it better match neuromorphic computing applications. An ultra low power and small size ring oscillator was designed to provide a global clock to all design blocks. Experimental results show that the average power consumption of the proposed router is 0.26mW, and only 0.01mW when idle. It occupies a much smaller area (0.007 mm 2) compared to other router designs described in previous works. It can be seen from the experimental results that after the clock gating circuitry is added, the total power consumption of 3 x 3 router array is significantly reduced, approximately 2.1 x lower when busy and 21 x lower when idle.