ZAMBEZI: a parallel pattern parallel fault sequential circuit fault simulator

• Published in: Proceedings of 14th VLSI Test Symposium pp. 438 - 443
• Main Authors: Amin, M.B., Vinnakota, B.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 1996
• Subjects: Acceleration; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Computer science; Computer simulation; Logic testing; Parallel processing; Sequential circuits
• DOI: 10.1109/VTEST.1996.510890
• ISBN: 9780818673047; 0818673044
• ISSN: 1093-0167

Sequential circuit fault simulators use the multiple bits in a computer data word to accelerate simulation. We introduce, and implement, a new sequential circuit fault simulator, a parallel pattern parallel fault simulator, ZAMBEZI, which simultaneously simulates multiple faults with multiple vectors in one data word. ZAMBEZI is developed by enhancing the control flow, of existing parallel pattern algorithms. For a very wide range of benchmark circuits, compared to parallel fault and parallel pattern simulators, ZAMBEZI offers either the best, or very close to the best, uniprocessor performance. ZAMBEZI also offers superior performance when parallelized.