Simulating the behaviour of software modules by trace rewriting

The trace assertion method is a module interface specification method based on the finite state machine model. To support this method, the authors plan to develop a specification simulation tool, a trace simulator, that symbolically interprets trace assertions of trace specifications and simulates t...

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Published inProceedings of 1993 15th International Conference on Software Engineering pp. 14 - 23
Main Authors Wang, Y., Parnas, D.L.
Format Conference Proceeding
LanguageEnglish
Published IEEE Comput. Soc. Press 1993
Subjects
Automata
Communication standards
Computational modeling
Computer simulation
Discrete event simulation
Formal specifications
History
Software systems
Software tools
Testing
Online AccessGet full text
ISBN9780818637001
0818637005
ISSN0270-5257
DOI10.1109/ICSE.1993.346059

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Abstract The trace assertion method is a module interface specification method based on the finite state machine model. To support this method, the authors plan to develop a specification simulation tool, a trace simulator, that symbolically interprets trace assertions of trace specifications and simulates the externally observable behavior of the modules specified. They first present the trace assertion method. Then trace rewriting systems are formally defined, and it is shown that trace rewriting, a technique similar to term rewriting, can be applied to implement trace simulation.< >
AbstractList The trace assertion method is a module interface specification method based on the finite state machine model. To support this method, the authors plan to develop a specification simulation tool, a trace simulator, that symbolically interprets trace assertions of trace specifications and simulates the externally observable behavior of the modules specified. They first present the trace assertion method. Then trace rewriting systems are formally defined, and it is shown that trace rewriting, a technique similar to term rewriting, can be applied to implement trace simulation.< >
Author Parnas, D.L.
Wang, Y.
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Snippet The trace assertion method is a module interface specification method based on the finite state machine model. To support this method, the authors plan to...
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StartPage 14
SubjectTerms Automata
Communication standards
Computational modeling
Computer simulation
Discrete event simulation
Formal specifications
History
Software systems
Software tools
Testing
Title Simulating the behaviour of software modules by trace rewriting
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