A new test generation methodology using selective clocking for the clock line controlled circuits

This paper presents a novel sequential test generation technique for circuits with clock line control (CLC). CLC is a design for testability (DFT) technique that can transform a complex test generation problem into multiple small ones that are efficiently manageable by selectively enabling or disabl...

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Bibliographic Details
Published inProceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors pp. 354 - 358
Main Authors Sanghyeon Baeg, Rogers, W.A.
Format Conference Proceeding
LanguageEnglish
Published IEEE Comput. Soc. Press 1994
Subjects
Circuit faults
Circuit testing
Clocks
Design for testability
Hardware
Semiconductor device testing
Sequential analysis
Sequential circuits
Synchronous generators
Tires
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Summary:This paper presents a novel sequential test generation technique for circuits with clock line control (CLC). CLC is a design for testability (DFT) technique that can transform a complex test generation problem into multiple small ones that are efficiently manageable by selectively enabling or disabling the synchronous operation of modules. The new test generation methodology for CLC circuits is smart enough to selectively clock modules, expand multiple time frames for a sequential module and compose these time frames to generate input and clock vectors for an entire circuit. Test generation for the ISCAS '89 circuits, with and without both CLC and scan has been performed. High fault coverage in a short time has been achieved using test generator with CLC.< >
ISBN:9780818665653
0818665653
DOI:10.1109/ICCD.1994.331925