Work in Progress: Automatic Construction of Pipeline Datapaths from High-Level HDL Code

• Published in: Proceedings / IEEE Real-Time and Embedded Technology and Applications Symposium pp. 305 - 308
• Main Authors: Bensaid, Samira Ait, Asavoae, Mihail, Thabet, Farhat, Jan, Mathieu
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.05.2022
• Subjects: Automation; Codes; Hardware; HDL languages; Manuals; pipeline datapath; Pipelines; processor design; Real-time systems; Timing; WCET analysis
• ISSN: 2642-7346
• DOI: 10.1109/RTAS54340.2022.00034

Safety-critical systems rely on worst-case timing analysis under architecture considerations to ensure that their timing bounds could be guaranteed. Usually, such architecture models are constructed by hand, from processor manuals. However, with open hardware initiatives and high-level Hardware Description Languages (HDL), automation would and should be possible. In this paper, we present an approach for constructing pipeline datapath models from processor designs described in high-level HDLs. We propose a methodology based on the Chisel/FIRRTL Hardware Compiler Framework and we report preliminary results on several open-source RISC-V processors.