Effect of cleaning and non-cleaning situations on the reliability of flip-chip packages

• Published in: Proceedings of 3rd International Conference on Adhesive Joining and Coating Technology in Electronics Manufacturing 1998 (Cat. No.98EX180) pp. 211 - 219
• Main Authors: Wang, J., Zou, D., Qian, Z., Ren, W., Liu, S., Dudderar, T.D., Sullivan, P.A.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 1998
• Subjects: Cleaning; Contamination; Flip chip solder joints; Interferometry; Packaging; Pollution measurement; Semiconductor device measurement; Soldering; Stress; Testing
• ISBN: 9780780349346; 0780349342
• DOI: 10.1109/ADHES.1998.742029

Experimental and numerical studies are conducted to investigate whether flip chip solder joint reliability is affected by noncleaning situations, in which underfill cannot be completely filled in solder ball corners due to contamination (e.g. flux residue) after reflow. Real-time moire interferometry is used to measure warpage for cleaning and noncleaning flip-chip package specimens during test, while a nonlinear FEA technique, where solder ball/underfill viscoplastic properties are considered, is adapted to simulate cleaning and noncleaning situations to assess impact on solder joint reliability. Results show that there is no obvious difference in warpage obtained from either test data or numerical work between cleaning samples and noncleaning samples. However, stress simulations reveal that the noncleaning situation decreases mechanical stability and shortens flip-chip package lifetime to a level well below that of cleaning simulation results. Fatigue life at some points of the outmost solder joint from cleaning FEA models is much higher that from noncleaning FEA models. As it is hard to find perfectly filled layers for any real world samples, the cleaning model yields overly conservative results. The predicted flip-chip package deformation values from the FEA are also compared with test data obtained from the laser moire interferometry technique. Good agreement is obtained. In particular, the flip-chip package displacement contours in both the x and y directions obtained from the test show similar distribution patterns to those modeled by the FEM.