On the Enhanced p‐Type Performance of Back‐Gated WS2 Devices - Marquez, Carlos; Gity, Farzan; Galdon, Jose C.; Martinez, Alberto; Salazar, Norberto; Ansari, Lida; Neill, Hazel; Donetti, Luca; Lorenzo, Francisco; Caño‐Garcia, Manuel; Ortega, Ruben; Navarro, Carlos; et al. (Advanced electronic materials, 2025)
In this work, a scalable technique is presented for the direct growth of tungsten disulfide (WS2) utilized in back‐gated field‐effect transistors (FETs), demonstrating robust and persistent p‐type behavior across diverse conditions. Notably, this p‐type behavior is consistently observed regardless of the metal contacts, semiconductor thickness, or ambient conditions, and remains stable even after high‐vacuum and high‐temperature annealing. Electrical characterization reveals negligible Fermi‐level pinning at the conduction band edge, with minimal Schottky barrier heights for hole carriers below 180 mV and a well‐defined thermionic transport regime. The devices exhibit field‐effect mobilities with a clear back‐gate dependence, reaching values up to 0.1 cm2V−1s−1. Temperature‐dependent transport analysis indicates that charge carrier mobility is predominantly limited by impurity scattering and Coulomb interactions. First‐principles simulations corroborate that the persistent p‐type behavior could be driven by the presence of tungsten vacancies or WO3 oxide species. This study highlights the potential of WS2 for scalable integration into advanced p‐type electronic devices and provides critical insights into the intrinsic mechanisms governing its charge transport properties. A scalable method for directly growing WS2 enables robust and persistent p‐type behavior in back‐gated FETs, independent of metal contacts, thickness, or ambient conditions. Electrical measurements reveal minimal Schottky barrier heights and stable thermionic transport, while first‐principles simulations suggest tungsten vacancies or WO3 species as the driving mechanism. These findings pave the way for WS2‐based p‐type electronics.