A 22-nm FD-SOI CMOS 7.5-9.6 GHz CP PLL Used in Wifi7 Achieved 56 fs-RMS-jitter and -65 dBc Spur

• Published in: Journal of semiconductor technology and science Vol. 25; no. 4; pp. 375 - 383
• Main Authors: She, Xu, Xie, Yisha, Liu, Lintao, Guo, Aiying
• Format: Journal Article
• Language: English
• Published: 대한전자공학회 31.08.2025
• Subjects: 전기공학
• DOI: 10.5573/JSTS.2025.25.4.375
• ISSN: 1598-1657

This brief presents a low-jitter Phase-Locked Loop (PLL) with dual paths and a negative Kv VoltageControlled Oscillator (NKvVCO) for a Wi-Fi 7 transceiver. The PLL employs a dual-path architecture to ensure robust lock retention under dramatic temperature variations, maintaining phase lock without loss of synchronization. Additionally, the design extends the tuning range of the charge pump (CP) while mitigating phase noise and preventing phase margin deterioration. Analytical expressions and simulations are derived to characterize the performance of this approach. In the locked state, the charge pump operates in a half-CP mode to achieve improved linearity and reduced phase noise. A negative Kv Voltage-Controlled Oscillator (NKvVCO) is used to overcome the limited control voltage range in a 22-nm Fully-Depleted Silicon-On-Insulator (FD-SOI) process. Prototyped in a 22-nm FD-SOI technology, the 7.5-9.6 GHz PLL demonstrates a spur of less than -65 dBc and a root-mean-square (rms) jitter of 57 fs. KCI Citation Count: 0