Efficient in situ learning of hybrid LIF neurons using WTA mechanism for high-speed low-power neuromorphic systems

• Published in: Physica scripta Vol. 99; no. 10; pp. 106010 - 106025
• Main Authors: Hussain, Syed Ali, Prasad V, P N S B S V, Sanki, Pradyut Kumar
• Format: Journal Article
• Language: English
• Published: IOP Publishing 01.10.2024
• Subjects: CNTFET; LIF Neuron; Memristor; Patterns recognition; SNN; WTA
• DOI: 10.1088/1402-4896/ad79c5
• ISSN: 0031-8949

Abstract The emerging market for hardware neuromorphic systems has fulfilled the growing demand for fast and energy-efficient computer architectures. Memristor-based neural networks are a viable approach to meet the need for low-power neuromorphic devices. Spiking neural networks (SNNs) are widely recognized as the best hardware solution for mimicking the brain’s efficient processing capabilities. To build the SNN model, we have designed an energy-efficient hybrid Leaky Integrated and Fire (LIF) neuron model using Carbon Nano Tube Field Effect Transistors (CNTFET) and memristors. This hybrid neuron operates at 3.89 MHz, with 1.047nW and 0.257fJ of power and energy per spike with a constant power supply (V dd ) and an excitation voltage of 0.5V, under the ideal conditions. When the intrinsic constraints of CNTFETs and memristors, such as parasitic elements and hysteresis effects, are taken into consideration, the operating frequency is lowered to 3.45 MHz (an 11.5% decrease), and energy consumption rises to 0.317 fJ per spike (a 23.3% increase). Despite these limitations, our design outperforms with existing works. On the other hand the development of in situ , Spike Timing Dependent Plasticity (STDP) learning through memristors as synapses results in a computational challenge. In this paper, we adopt a potent technique capable of carrying out both learning and inference. The weight modulation is accomplished using a linear memristor model, resulting in high speed and reduced power consumption. We intend to apply the winner-takes-all (WTA) mechanism within the SNN architecture, which incorporates recurrently connected proposed neurons in the output layer, for real-time pattern recognition. The proposed design has been implemented and the performance metrics superseded the existing works in terms of power, energy, and accuracy. Furthermore, the design is capable of classifying 50×10 4 images per second.