Two-rank Decimation Technique for High-speed Time-interleaved Analog-to-digital Converters

This paper proposes a two-rank decimation technique for high-speed time-interleaved (TI) analog-todigital converters (ADCs) to reduce the multiplexer (MUX) speed burden and enable real-time measurements while minimizing area requirements. The proposed architecture can alleviate the speed burden of d...

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Bibliographic Details
Published inJournal of semiconductor technology and science Vol. 25; no. 3; pp. 284 - 291
Main Authors Oh, Sang-won, Oh, Dong-Ryeol
Format Journal Article
LanguageEnglish
Published 대한전자공학회 30.06.2025
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