Two-rank Decimation Technique for High-speed Time-interleaved Analog-to-digital Converters

• Published in: Journal of semiconductor technology and science Vol. 25; no. 3; pp. 284 - 291
• Main Authors: Oh, Sang-won, Oh, Dong-Ryeol
• Format: Journal Article
• Language: English
• Published: 대한전자공학회 30.06.2025
• Subjects: 전기공학
• DOI: 10.5573/JSTS.2025.25.3.284
• ISSN: 1598-1657

This paper proposes a two-rank decimation technique for high-speed time-interleaved (TI) analog-todigital converters (ADCs) to reduce the multiplexer (MUX) speed burden and enable real-time measurements while minimizing area requirements. The proposed architecture can alleviate the speed burden of decimation and MUX circuits to a level comparable to that of a single-channel ADC by passing the digital outputs of each channel through a sequential decimation circuit before being merged in the MUX. The design was validated using a 6-bit 20 GS/s TI ADC implemented in a 40 nm CMOS process. The active area of the proposed two-rank decimation circuit is about 0.007 mm2 , which is only 8% compared to the memory-based approach of 0.09 mm2 . The power consumption of the proposed two-rank decimation circuit is 0.78 mW under a supply voltage of 0.9 V and with a 20 GS/s conversion speed, the measured signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are 30.12 and 40.23 dB, respectively. KCI Citation Count: 0