APA (7th ed.) Citation

Park, J., Choi, D., & Kim, H. (2025). RADAR: An Efficient FPGA-based ResNet Accelerator with Data-aware Reordering of Processing Sequences. Journal of semiconductor technology and science, 25(4), 451-458. https://doi.org/10.5573/JSTS.2025.25.4.451

Chicago Style (17th ed.) Citation

Park, Juntae, Dahun Choi, and Hyun Kim. "RADAR: An Efficient FPGA-based ResNet Accelerator with Data-aware Reordering of Processing Sequences." Journal of Semiconductor Technology and Science 25, no. 4 (2025): 451-458. https://doi.org/10.5573/JSTS.2025.25.4.451.

MLA (9th ed.) Citation

Park, Juntae, et al. "RADAR: An Efficient FPGA-based ResNet Accelerator with Data-aware Reordering of Processing Sequences." Journal of Semiconductor Technology and Science, vol. 25, no. 4, 2025, pp. 451-458, https://doi.org/10.5573/JSTS.2025.25.4.451.