A Describing Method of an Image Processing Software in C for a High-Level Synthesis Considering a Function Chaining

• Published in: IEICE Transactions on Information and Systems Vol. E101.D; no. 2; pp. 324 - 334
• Main Authors: YAMAWAKI, Akira, SERIKAWA, Seiichi
• Format: Journal Article
• Language: English
• Published: Tokyo The Institute of Electronics, Information and Communication Engineers 01.01.2018; Japan Science and Technology Agency
• Subjects: Central processing units; Chaining; Chains; Co-design; CPUs; describing method; Edge detection; Embedded systems; Filtration; FPGA; function chaining; Hardware; High level synthesis; Image processing; Levels; Microprocessors; Performance degradation; Pixels; Software

This paper shows a describing method of an image processing software in C for high-level synthesis (HLS) technology considering function chaining to realize an efficient hardware. A sophisticated image processing would be built on the sequence of several primitives represented as sub-functions like...