Evaluating Energy-Efficiency of DRAM Channel Interleaving Schemes for Multithreaded Programs
The power consumption of server platforms has been increasing as the amount of hardware resources equipped on them is increased. Especially, the capacity of DRAM continues to grow, and it is not rare that DRAM consumes higher power than processors on modern servers. Therefore, a reduction in the DRA...
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| Published in | IEICE Transactions on Information and Systems Vol. E101.D; no. 9; pp. 2247 - 2257 |
|---|---|
| Main Authors | , , , , , |
| Format | Journal Article |
| Language | English |
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Tokyo
The Institute of Electronics, Information and Communication Engineers
01.09.2018
Japan Science and Technology Agency |
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| Abstract | The power consumption of server platforms has been increasing as the amount of hardware resources equipped on them is increased. Especially, the capacity of DRAM continues to grow, and it is not rare that DRAM consumes higher power than processors on modern servers. Therefore, a reduction in the DRAM energy consumption is a critical challenge to reduce the system-level energy consumption. Although it is well known that improving row buffer locality(RBL) and bank-level parallelism (BLP) is effective to reduce the DRAM energy consumption, our preliminary evaluation on a real server demonstrates that RBL is generally low across 15 multithreaded benchmarks. In this paper, we investigate the memory access patterns of these benchmarks using a simulator and observe that cache line-grained channel interleaving schemes, which are widely applied to modern servers including multiple memory channels, hurt the RBL each of the benchmarks potentially possesses. In order to address this problem, we focus on a row-grained channel interleaving scheme and compare it with three cache line-grained schemes. Our evaluation shows that it reduces the DRAM energy consumption by 16.7%, 12.3%, and 5.5% on average (up to 34.7%, 28.2%, and 12.0%) compared to the other schemes, respectively. |
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| AbstractList | The power consumption of server platforms has been increasing as the amount of hardware resources equipped on them is increased. Especially, the capacity of DRAM continues to grow, and it is not rare that DRAM consumes higher power than processors on modern servers. Therefore, a reduction in the DRAM energy consumption is a critical challenge to reduce the system-level energy consumption. Although it is well known that improving row buffer locality(RBL) and bank-level parallelism (BLP) is effective to reduce the DRAM energy consumption, our preliminary evaluation on a real server demonstrates that RBL is generally low across 15 multithreaded benchmarks. In this paper, we investigate the memory access patterns of these benchmarks using a simulator and observe that cache line-grained channel interleaving schemes, which are widely applied to modern servers including multiple memory channels, hurt the RBL each of the benchmarks potentially possesses. In order to address this problem, we focus on a row-grained channel interleaving scheme and compare it with three cache line-grained schemes. Our evaluation shows that it reduces the DRAM energy consumption by 16.7%, 12.3%, and 5.5% on average (up to 34.7%, 28.2%, and 12.0%) compared to the other schemes, respectively. |
| Author | ONO, Takatsugu YASUI, Yuichiro INOUE, Koji SASAKI, Hiroshi IMAMURA, Satoshi FUJISAWA, Katsuki |
| Author_xml | – sequence: 1 fullname: IMAMURA, Satoshi organization: Fujitsu Laboratories Ltd – sequence: 2 fullname: YASUI, Yuichiro organization: Institute of Mathematics for Industry, Kyushu University – sequence: 3 fullname: INOUE, Koji organization: Faculty of Information Science and Electrical Engineering, Kyushu University – sequence: 4 fullname: ONO, Takatsugu organization: Faculty of Information Science and Electrical Engineering, Kyushu University – sequence: 5 fullname: SASAKI, Hiroshi organization: Department of Computer Science, Columbia University – sequence: 6 fullname: FUJISAWA, Katsuki organization: Institute of Mathematics for Industry, Kyushu University |
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| Cites_doi | 10.1145/360128.360134 10.1145/2155620.2155624 10.1109/ASAP.2014.6868669 10.1109/MICRO.2010.51 10.1145/2451116.2451137 10.1145/1736020.1736045 10.1145/2024724.2024954 10.1145/339647.339668 10.1109/HPGDMP.2016.010 10.1145/2370816.2370869 10.1109/ISLPED.2011.5993649 10.1145/2989081.2989131 10.1145/2145816.2145840 10.1109/MICRO.2016.7783760 10.1145/2513228.2513306 10.1109/L-CA.2011.4 10.1109/HPCA.2014.6835945 10.1109/HPCA.2012.6168944 10.1109/MICRO.2007.4408252 10.1109/ICPPW.2010.38 10.1145/2155620.2155664 10.1145/1840845.1840883 10.1145/2915516.2915522 |
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| Copyright | 2018 The Institute of Electronics, Information and Communication Engineers Copyright Japan Science and Technology Agency 2018 |
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| SubjectTerms | address mapping schemes Benchmarks DRAM Energy consumption energy efficiency Energy management Power consumption Power management |
| Title | Evaluating Energy-Efficiency of DRAM Channel Interleaving Schemes for Multithreaded Programs |
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