Repeatable, accurate, and high speed multi-level programming of memristor 1T1R arrays for power efficient analog computing applications

• Published in: Nanotechnology Vol. 27; no. 36; p. 365202
• Main Authors: Merced-Grafals, Emmanuelle J, Dávila, Noraica, Ge, Ning, Williams, R Stanley, Strachan, John Paul
• Format: Journal Article
• Language: English
• Published: England IOP Publishing 09.09.2016
• Subjects: accelerators; algorithm; Algorithms; analog computing; Arrays; Conductance; dot product engine; Gates; Memory devices; memristor; multi-level cell; Programming; Resistors; Transistors
• DOI: 10.1088/0957-4484/27/36/365202
• ISSN: 0957-4484

Beyond use as high density non-volatile memories, memristors have potential as synaptic components of neuromorphic systems. We investigated the suitability of tantalum oxide (TaOx) transistor-memristor (1T1R) arrays for such applications, particularly the ability to accurately, repeatedly, and rapidly reach arbitrary conductance states. Programming is performed by applying an adaptive pulsed algorithm that utilizes the transistor gate voltage to control the SET switching operation and increase programming speed of the 1T1R cells. We show the capability of programming 64 conductance levels with <0.5% average accuracy using 100 ns pulses and studied the trade-offs between programming speed and programming error. The algorithm is also utilized to program 16 conductance levels on a population of cells in the 1T1R array showing robustness to cell-to-cell variability. In general, the proposed algorithm results in approximately 10× improvement in programming speed over standard algorithms that do not use the transistor gate to control memristor switching. In addition, after only two programming pulses (an initialization pulse followed by a programming pulse), the resulting conductance values are within 12% of the target values in all cases. Finally, endurance of more than 106 cycles is shown through open-loop (single pulses) programming across multiple conductance levels using the optimized gate voltage of the transistor. These results are relevant for applications that require high speed, accurate, and repeatable programming of the cells such as in neural networks and analog data processing.