A Method for Diagnosing Bridging Fault between a Gate Signal Line and a Clock Line

In this paper, we propose a method to diagnose a bridging fault between a clock line and a gate signal line. Assuming that scan based flush tests are applied, we perform fault simulation to deduce candidate faults. By analyzing fault behavior, it is revealed that faulty clock waveforms depend on the...

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Bibliographic Details
Published inIEICE Transactions on Information and Systems Vol. E100.D; no. 9; pp. 2224 - 2227
Main Authors HIGAMI, Yoshinobu, WANG, Senling, TAKAHASHI, Hiroshi, KOBAYASHI, Shin-ya, SALUJA, Kewal K.
Format Journal Article
LanguageEnglish
Published Tokyo The Institute of Electronics, Information and Communication Engineers 01.01.2017
Japan Science and Technology Agency
Subjects
Bridging faults
clock lines
Fault diagnosis
Waveforms
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Summary:In this paper, we propose a method to diagnose a bridging fault between a clock line and a gate signal line. Assuming that scan based flush tests are applied, we perform fault simulation to deduce candidate faults. By analyzing fault behavior, it is revealed that faulty clock waveforms depend on the timing of the signal transition on a gate signal line which is bridged. In the fault simulation, a backward sensitized path tracing approach is introduced to calculate the timing of signal transitions. Experimental results show that the proposed method deduces candidate faults more accurately than our previous method.
ISSN:0916-8532
1745-1361
DOI:10.1587/transinf.2016EDL8210