Optimal Architecture of Floating-Point Arithmetic for Neural Network Training Processors

• Published in: Sensors (Basel, Switzerland) Vol. 22; no. 3; p. 1230
• Main Authors: Junaid, Muhammad, Arslan, Saad, Lee, TaeGeon, Kim, HyungWon
• Format: Journal Article
• Language: English
• Published: Switzerland MDPI AG 06.02.2022; MDPI
• Subjects: Accuracy; Algorithms; Approximation; Artificial Intelligence; Back propagation; Brain; Computer architecture; convolutional neural network (CNN); Data processing; Energy consumption; Floating point arithmetic; floating-points; Format; IEEE 754; Inference; Internet of Things; MNIST dataset; Neural networks; Neural Networks, Computer; Power management; Probability; Probability distribution; Processors; Semiconductors; Supervised Machine Learning; floating-points; convolutional neural network (CNN); MNIST dataset; IEEE 754
• DOI: 10.3390/s22031230
• ISSN: 1424-8220

The convergence of artificial intelligence (AI) is one of the critical technologies in the recent fourth industrial revolution. The AIoT (Artificial Intelligence Internet of Things) is expected to be a solution that aids rapid and secure data processing. While the success of AIoT demanded low-power neural network processors, most of the recent research has been focused on accelerator designs only for inference. The growing interest in self-supervised and semi-supervised learning now calls for processors offloading the training process in addition to the inference process. Incorporating training with high accuracy goals requires the use of floating-point operators. The higher precision floating-point arithmetic architectures in neural networks tend to consume a large area and energy. Consequently, an energy-efficient/compact accelerator is required. The proposed architecture incorporates training in 32 bits, 24 bits, 16 bits, and mixed precisions to find the optimal floating-point format for low power and smaller-sized edge device. The proposed accelerator engines have been verified on FPGA for both inference and training of the MNIST image dataset. The combination of 24-bit custom FP format with 16-bit Brain FP has achieved an accuracy of more than 93%. ASIC implementation of this optimized mixed-precision accelerator using TSMC 65nm reveals an active area of 1.036 × 1.036 mm and energy consumption of 4.445 µJ per training of one image. Compared with 32-bit architecture, the size and the energy are reduced by 4.7 and 3.91 times, respectively. Therefore, the CNN structure using floating-point numbers with an optimized data path will significantly contribute to developing the AIoT field that requires a small area, low energy, and high accuracy.