A Survey of Hardware Self-Organizing Maps

• Published in: IEEE transaction on neural networks and learning systems Vol. 34; no. 11; pp. 8154 - 8173
• Main Authors: Jovanovic, Slavisa, Hikawa, Hiroomi
• Format: Journal Article
• Language: English
• Published: United States IEEE 01.11.2023; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Application-specific integrated circuit (ASIC); Artificial intelligence; Big Data; Clustering; Clustering algorithms; Computer architecture; Computer Science; Data reduction; Design optimization; Feature maps; field-programmable gate array (FPGA); Graphics processing units; Hardware; Internet of Things; Neurons; Optimization techniques; real time; Self organizing maps; Self-organizing feature maps; self-organizing map; survey; Surveys; Systems design; Topology; Training; Unsupervised learning; vector quantization
• ISSN: 2162-237X; 2162-2388; 2162-2388
• DOI: 10.1109/TNNLS.2022.3152690

Self-organizing feature maps (SOMs) are commonly used technique for clustering and data dimensionality reduction in many application fields. Indeed, their inherent property of topology preservation and unsupervised learning of processed data without any prior knowledge put them in the front of candidates for data reduction in the Internet of Things (IoT) and big data (BD) technologies. However, the high computational cost of SOMs limits their use to offline approaches and makes the online real-time high-performance SOM processing more challenging and mostly reserved to specific hardware implementations. In this article, we present a survey of hardware (HW) SOM implementations found in the literature so far: the most widely used computing blocks, architectures, design choices, adaptation, and optimization techniques that have been reported in the field of hardware SOMs. Moreover, we give an overview of main challenges and trends for their ubiquitous adoption as hardware accelerators in many application fields. This article is expected to be useful for researchers in the areas of artificial intelligence, hardware architecture, and system design.