Recent progress in integration of III-V nanowire transistors on Si substrate by selective-area growth

• Published in: Journal of physics. D, Applied physics Vol. 47; no. 39; pp. 394001 - 13
• Main Authors: Tomioka, Katsuhiro, Fukui, Takashi
• Format: Journal Article
• Language: English
• Published: IOP Publishing 01.10.2014
• Subjects: Construction; Dislocations; Electronics; epitaxy; FET; Field effect transistors; III-V nanowires; Nanowires; Semiconductor devices; Silicon; Silicon substrates; tunnel FET
• ISSN: 0022-3727; 1361-6463
• DOI: 10.1088/0022-3727/47/39/394001

We report on the recent progress in electronic applications using III-V nanowires (NWs) on Si substrates using the selective-area growth method. This method could align vertical III-V NWs on Si under specific growth conditions. Detailed studies of the III-V NW/Si heterointerface showed the possibility of achieving coherent growth regardless of misfit dislocations in the III-V/Si heterojunction. The vertical III-V NWs grown using selective-area growth were utilized for high performance vertical field-effect transistors (FETs). Furthermore, III-V NW/Si heterointerfaces with fewer misfit dislocations provided us with a unique band discontinuity with a new functionality that can be used for the application of tunnel diodes and tunnel FETs. These demonstrations could open the door to a new approach for creating low power switches using III-V NWs as building-blocks of future nanometre-scaled electronic circuits on Si platforms.