A Preemption Algorithm for a Multitasking Environment on Dynamically Reconfigurable Processors
Task preemption is a critical mechanism for building an effective multi-tasking environment on dynamically reconfigurable processors. When a task is preempted, its necessary state information must be correctly preserved in order for the task to be resumed later. Not only do coarse-grained Dynamicall...
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| Published in | IEICE Transactions on Information and Systems Vol. E91.D; no. 12; pp. 2793 - 2803 |
|---|---|
| Main Authors | , |
| Format | Journal Article |
| Language | English |
| Published |
Oxford
The Institute of Electronics, Information and Communication Engineers
2008
Oxford University Press |
| Subjects | |
| Online Access | Get full text |
| ISSN | 0916-8532 1745-1361 1745-1361 |
| DOI | 10.1093/ietisy/e91-d.12.2793 |
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| Abstract | Task preemption is a critical mechanism for building an effective multi-tasking environment on dynamically reconfigurable processors. When a task is preempted, its necessary state information must be correctly preserved in order for the task to be resumed later. Not only do coarse-grained Dynamically Reconfigurable Processing Array (DRPAs) devices have different architectures using a variety of development tools, but the great amount of state data of hardware tasks executing on such devices are usually distributed on many different storage elements. To address these difficulties, this paper aims at studying a general method for capturing the state data of hardware tasks targeting coarse-grained DRPAs. Based on resource usage, algorithms for identifying preemption points and inserting preemption states subject to user-specified preemption latency are proposed. Moreover, a modification to automatically incorporate proposed steps into the system design flow is also discussed. The performance degradation caused by additional preemption states is minimized by allowing preemption only at predefined points where demanded resources are small. The evaluation result using a model based on NEC Electronics' DRP-1 shows that the proposed method can produce preemption points satisfying a given preemption latency with reasonable hardware overhead (from 6% to 15%). |
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| AbstractList | Task preemption is a critical mechanism for building an effective multi-tasking environment on dynamically reconfigurable processors. When a task is preempted, its necessary state information must be correctly preserved in order for the task to be resumed later. Not only do coarse-grained Dynamically Reconfigurable Processing Array (DRPAs) devices have different architectures using a variety of development tools, but the great amount of state data of hardware tasks executing on such devices are usually distributed on many different storage elements. To address these difficulties, this paper aims at studying a general method for capturing the state data of hardware tasks targeting coarse-grained DRPAs. Based on resource usage, algorithms for identifying preemption points and inserting preemption states subject to user-specified preemption latency are proposed. Moreover, a modification to automatically incorporate proposed steps into the system design flow is also discussed. The performance degradation caused by additional preemption states is minimized by allowing preemption only at predefined points where demanded resources are small. The evaluation result using a model based on NEC Electronics' DRP-1 shows that the proposed method can produce preemption points satisfying a given preemption latency with reasonable hardware overhead (from 6% to 15%). |
| Author | AMANO, Hideharu TUAN, Vu Manh |
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| Keywords | Degradation Performance evaluation Processor hardware overhead dynamically reconfigurable processor preemption latency Integrated circuit System design preemption algorithm Reconfigurable architectures Algorithm Damaging |
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| References | [16] V. Nollet, P. Coene, D. Verkest, S. Vernalde, and R. Lauwereins, “Designing an operating system for a heterogeneous reconfigurable SoC, ” Proc. International Parallel and Distributed Processing Symposium, Paris, June 2003. [22] MPEG Software Simulation Group (MSSG), http://www.mpeg.org/MPEG/MSSG [5] H. Simmler, L. Levinson, and R. Manner, “Multitasking on FPGA coprocessors, ” Proc. 10th International Workshop on FPGAs, pp.121-130, 2000. [10] D. Koch, C. Haubelt, and J. Teich, “Efficient hardware checkpointing: Concepts, overhead analysis, and implementation, ” Proc. FPGA, pp.188-196, Feb. 2007. [19] V. Sreedhar, G.R. Gao, and Y. Lee, “Identifying loops using DJ graphs, ” ACM Trans. Programming Languages and Systems (TOPLAS), vol.18, no.6, pp.649-658, Nov. 1996. [13] M. Motomura, “A dynamically reconfigurable processor architecture, ” Microprocessor Forum, Oct. 2002. [14] T. Toi, N. Nakamura, Y. Kato, T. Awashima, and K. Wakabayashi, “High-level synthesis challenges and solutions for a dynamically reconfigurable processor, ” Proc. CICC, Nov. 2006. [2] J. Noguera and R.M. Badia, “Multitasking on reconfigurable architectures: Microarchitecture support and dynamic scheduling, ” ACM Trans. Embedded Computing Systems, vol.3, no.2, pp.385-406, 2004. [9] H. Kalte and M. Porrmann, “Context saving and restoring for multitasking in reconfigurable systems, ” Proc. 15th International Conference on FPL, pp.223-228, Aug. 2005. [7] L. Levinson, R. Manner, M. Sesler, and H. Simmler, “Preemptive multitasking on FPGAs, ” Proc. 2000 IEEE Symposium on FCCM, 2000. [20] M. Suzuki, Y. Hasegawa, Y. Yamada, N. Kaneko, K. Deguchi, H. Amano, K. Anjo, M. Motomura, K. Wakabayashi, T. Toi, and T. Awashima, “Stream applications on the dynamically reconfigurable processor, ” Proc. International Conference on FPT, pp.137-144, Dec. 2004. [18] A.V. Aho, R. Sethi, and J.D. Ullman, Compiler: Principles, Techniques, and Tools, Addison Wesley, 1986. [4] J.S.N. Jean, K. Tomko, V. Yavagal, J. Shah, and R. Cook, “Dynamic reconfiguration to support concurrent applications, ” IEEE Trans. Comput., vol.48, no.6, pp.591-602, June 1999. [12] M. Ullmann, M. Huebner, B. Grimm, and J. Becker, “An FPGA run-time system for dynamical on-demand reconfiguration, ” Proc. 11th Reconfigurable Architectures Workshop (RAW), April 2004. [11] S. Jovanovic, C. Tanougast, and S. Weber, “A hardware preemptive multitasking mechanism based on scan-path register structure for FPGA-based reconfigurable systems, ” Proc. NASA/ESA Conference on AHS, pp.358-364, Aug. 2007. [3] K. Kim, R. Karri, and M. Potkonjak, “Micropreemption synthesis: An enabling mechanism for multitask VLSI systems, ” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol.25, no.1, pp.19-30, Jan. 2006. [8] S.A. Guccione, D. Levi, and P. Sundararajan, “JBits: A Java-based interface for reconfigurable computing, ” Proc. Second Annual Military and Aerospace Applications of Programmable Devices and Technologies Conference (MAPLD), Sept. 1999. [21] Independent JPEG Group, http://www.ijg.org [6] G. Brebner, “The swappable logic unit: A paradigm for virtual hardware, ” IEEE Symposium on FPGAs for CCMs, pp.77-86, 1997. [15] J. Simonson and J.H. Patel, “Use of preferred preemption points in cache-based real-time systems, ” Proc. International Computer Performance and Dependability Symposium, pp.316-325, April 1995. [17] E.A. Lee and D.C. Messerschmitt, “Static scheduling of synchronous data flow programs for digital signal processing, ” IEEE Trans. Comput., vol.36, no.1, pp.24-36, 1987. [23] C. Berrou and A. Glavieux, “Near optimum error correcting coding and decoding: Turbo codes, ” IEEE Trans. Commun., vol.44, no.10, pp.1261-1271, Oct. 1996. [1] H. Amano, “A survey on dynamically reconfigurable processors, ” IEICE Trans. Commun., vol.E89-B, no.12, pp.3179-3187, Dec. 2006. |
| References_xml | – reference: [4] J.S.N. Jean, K. Tomko, V. Yavagal, J. Shah, and R. Cook, “Dynamic reconfiguration to support concurrent applications, ” IEEE Trans. Comput., vol.48, no.6, pp.591-602, June 1999. – reference: [7] L. Levinson, R. Manner, M. Sesler, and H. Simmler, “Preemptive multitasking on FPGAs, ” Proc. 2000 IEEE Symposium on FCCM, 2000. – reference: [22] MPEG Software Simulation Group (MSSG), http://www.mpeg.org/MPEG/MSSG – reference: [11] S. Jovanovic, C. Tanougast, and S. Weber, “A hardware preemptive multitasking mechanism based on scan-path register structure for FPGA-based reconfigurable systems, ” Proc. NASA/ESA Conference on AHS, pp.358-364, Aug. 2007. – reference: [17] E.A. Lee and D.C. Messerschmitt, “Static scheduling of synchronous data flow programs for digital signal processing, ” IEEE Trans. Comput., vol.36, no.1, pp.24-36, 1987. – reference: [12] M. Ullmann, M. Huebner, B. Grimm, and J. Becker, “An FPGA run-time system for dynamical on-demand reconfiguration, ” Proc. 11th Reconfigurable Architectures Workshop (RAW), April 2004. – reference: [5] H. Simmler, L. Levinson, and R. Manner, “Multitasking on FPGA coprocessors, ” Proc. 10th International Workshop on FPGAs, pp.121-130, 2000. – reference: [16] V. Nollet, P. Coene, D. Verkest, S. Vernalde, and R. Lauwereins, “Designing an operating system for a heterogeneous reconfigurable SoC, ” Proc. International Parallel and Distributed Processing Symposium, Paris, June 2003. – reference: [2] J. Noguera and R.M. Badia, “Multitasking on reconfigurable architectures: Microarchitecture support and dynamic scheduling, ” ACM Trans. Embedded Computing Systems, vol.3, no.2, pp.385-406, 2004. – reference: [3] K. Kim, R. Karri, and M. Potkonjak, “Micropreemption synthesis: An enabling mechanism for multitask VLSI systems, ” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol.25, no.1, pp.19-30, Jan. 2006. – reference: [6] G. Brebner, “The swappable logic unit: A paradigm for virtual hardware, ” IEEE Symposium on FPGAs for CCMs, pp.77-86, 1997. – reference: [9] H. Kalte and M. Porrmann, “Context saving and restoring for multitasking in reconfigurable systems, ” Proc. 15th International Conference on FPL, pp.223-228, Aug. 2005. – reference: [1] H. Amano, “A survey on dynamically reconfigurable processors, ” IEICE Trans. Commun., vol.E89-B, no.12, pp.3179-3187, Dec. 2006. – reference: [19] V. Sreedhar, G.R. Gao, and Y. Lee, “Identifying loops using DJ graphs, ” ACM Trans. Programming Languages and Systems (TOPLAS), vol.18, no.6, pp.649-658, Nov. 1996. – reference: [8] S.A. Guccione, D. Levi, and P. Sundararajan, “JBits: A Java-based interface for reconfigurable computing, ” Proc. Second Annual Military and Aerospace Applications of Programmable Devices and Technologies Conference (MAPLD), Sept. 1999. – reference: [15] J. Simonson and J.H. Patel, “Use of preferred preemption points in cache-based real-time systems, ” Proc. International Computer Performance and Dependability Symposium, pp.316-325, April 1995. – reference: [21] Independent JPEG Group, http://www.ijg.org/ – reference: [13] M. Motomura, “A dynamically reconfigurable processor architecture, ” Microprocessor Forum, Oct. 2002. – reference: [20] M. Suzuki, Y. Hasegawa, Y. Yamada, N. Kaneko, K. Deguchi, H. Amano, K. Anjo, M. Motomura, K. Wakabayashi, T. Toi, and T. Awashima, “Stream applications on the dynamically reconfigurable processor, ” Proc. International Conference on FPT, pp.137-144, Dec. 2004. – reference: [23] C. Berrou and A. Glavieux, “Near optimum error correcting coding and decoding: Turbo codes, ” IEEE Trans. Commun., vol.44, no.10, pp.1261-1271, Oct. 1996. – reference: [14] T. Toi, N. Nakamura, Y. Kato, T. Awashima, and K. Wakabayashi, “High-level synthesis challenges and solutions for a dynamically reconfigurable processor, ” Proc. CICC, Nov. 2006. – reference: [10] D. Koch, C. Haubelt, and J. Teich, “Efficient hardware checkpointing: Concepts, overhead analysis, and implementation, ” Proc. FPGA, pp.188-196, Feb. 2007. – reference: [18] A.V. Aho, R. Sethi, and J.D. Ullman, Compiler: Principles, Techniques, and Tools, Addison Wesley, 1986. |
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| SubjectTerms | Algorithms Applied sciences Arrays Coarsening Design. Technologies. Operation analysis. Testing Devices dynamically reconfigurable processor Electronics Exact sciences and technology Hardware hardware overhead Integrated circuits Integrated circuits by function (including memories and processors) Mathematical models Multitasking preemption algorithm preemption latency Processors Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Tasks |
| Title | A Preemption Algorithm for a Multitasking Environment on Dynamically Reconfigurable Processors |
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