A Preemption Algorithm for a Multitasking Environment on Dynamically Reconfigurable Processors

• Published in: IEICE Transactions on Information and Systems Vol. E91.D; no. 12; pp. 2793 - 2803
• Main Authors: AMANO, Hideharu, TUAN, Vu Manh
• Format: Journal Article
• Language: English
• Published: Oxford The Institute of Electronics, Information and Communication Engineers 2008; Oxford University Press
• Subjects: Algorithms; Applied sciences; Arrays; Coarsening; Design. Technologies. Operation analysis. Testing; Devices; dynamically reconfigurable processor; Electronics; Exact sciences and technology; Hardware; hardware overhead; Integrated circuits; Integrated circuits by function (including memories and processors); Mathematical models; Multitasking; preemption algorithm; preemption latency; Processors; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Tasks; Degradation; Performance evaluation; Processor; hardware overhead; dynamically reconfigurable processor; preemption latency; Integrated circuit; System design; preemption algorithm; Reconfigurable architectures; Algorithm; Damaging
• ISSN: 0916-8532; 1745-1361; 1745-1361
• DOI: 10.1093/ietisy/e91-d.12.2793

Task preemption is a critical mechanism for building an effective multi-tasking environment on dynamically reconfigurable processors. When a task is preempted, its necessary state information must be correctly preserved in order for the task to be resumed later. Not only do coarse-grained Dynamically Reconfigurable Processing Array (DRPAs) devices have different architectures using a variety of development tools, but the great amount of state data of hardware tasks executing on such devices are usually distributed on many different storage elements. To address these difficulties, this paper aims at studying a general method for capturing the state data of hardware tasks targeting coarse-grained DRPAs. Based on resource usage, algorithms for identifying preemption points and inserting preemption states subject to user-specified preemption latency are proposed. Moreover, a modification to automatically incorporate proposed steps into the system design flow is also discussed. The performance degradation caused by additional preemption states is minimized by allowing preemption only at predefined points where demanded resources are small. The evaluation result using a model based on NEC Electronics' DRP-1 shows that the proposed method can produce preemption points satisfying a given preemption latency with reasonable hardware overhead (from 6% to 15%).