Efficient FPGA Implementation of a Dual-Frequency GNSS Receiver with Robust Inter-Frequency Aiding

• Published in: Sensors (Basel, Switzerland) Vol. 21; no. 14; p. 4634
• Main Authors: Huang, Kuan-Ying, Juang, Jyh-Ching, Tsai, Yung-Fu, Lin, Chen-Tsung
• Format: Journal Article
• Language: English
• Published: Switzerland MDPI AG 06.07.2021; MDPI
• Subjects: FPGA receiver implementation; interference; multi-frequency GNSS; Noise; Receivers & amplifiers; robust signal combination; robust statistical signal processing; Signal processing; FPGA receiver implementation; interference; multi-frequency GNSS; robust signal combination; robust statistical signal processing
• ISSN: 1424-8220; 1424-8220
• DOI: 10.3390/s21144634

Multiple frequency global navigation satellite system (GNSS) has become more complex due to the existence of extra channels. Typically, auxiliary methods are used to synchronize the second signals at other bands by aiding the acquired channel parameters. However, there are critical limitations because the reception of GNSS signals is subject to uncertainties due to noise carrier injection or circuit interference. The relationship between the two Doppler frequencies can be affected by uncertainties. Therefore, we aimed to implement an efficient dual-frequency field-programmable gate array (FPGA), performing a direct aid tracking method for the secondary channel to achieve resource efficiency and inner aid robustness. A robust estimator that directly links two loops in the two bands is proposed. In this scheme, (1) a robust estimator able to cope with uncertainty; (2) a primary tracking scheme to obtain the error boundary, and (3) a tracked bit-boundary for the initial code phase of the second channel are used. Based on experiments on the FPGA, the robust channel link can achieve direct aid tracking, and 31.02% of the original hardware resources from the aided acquisition module were released satisfactorily.