Optimization of Structure and Electrical Characteristics for Four-Layer Vertically-Stacked Horizontal Gate-All-Around Si Nanosheets Devices
In this paper, the optimizations of vertically-stacked horizontal gate-all-around (GAA) Si nanosheet (NS) transistors on bulk Si substrate are systemically investigated. The release process of NS channels was firstly optimized to achieve uniform device structures. An over 100:1 selective wet-etch ra...
Saved in:
| Published in | Nanomaterials (Basel, Switzerland) Vol. 11; no. 3; p. 646 |
|---|---|
| Main Authors | , , , , , , , , , , , , , , , , , , |
| Format | Journal Article |
| Language | English |
| Published |
Switzerland
MDPI
05.03.2021
MDPI AG |
| Subjects | |
| Online Access | Get full text |
Cover
Loading…
| Abstract | In this paper, the optimizations of vertically-stacked horizontal gate-all-around (GAA) Si nanosheet (NS) transistors on bulk Si substrate are systemically investigated. The release process of NS channels was firstly optimized to achieve uniform device structures. An over 100:1 selective wet-etch ratio of GeSi to Si layer was achieved for GeSi/Si stacks samples with different GeSi thickness (5 nm, 10 nm, and 20 nm) or annealing temperatures (≤900 °C). Furthermore, the influence of ground-plane (GP) doping in Si sub-fin region to improve electrical characteristics of devices was carefully investigated by experiment and simulations. The subthreshold characteristics of n-type devices were greatly improved with the increase of GP doping doses. However, the p-type devices initially were improved and then deteriorated with the increase of GP doping doses, and they demonstrated the best electrical characteristics with the GP doping concentrations of about 1 × 1018 cm−3, which was also confirmed by technical computer aided design (TCAD) simulation results. Finally, 4 stacked GAA Si NS channels with 6 nm in thickness and 30 nm in width were firstly fabricated on bulk substrate, and the performance of the stacked GAA Si NS devices achieved a larger ION/IOFF ratio (3.15 × 105) and smaller values of Subthreshold swings (SSs) (71.2 (N)/78.7 (P) mV/dec) and drain-induced barrier lowering (DIBLs) (9 (N)/22 (P) mV/V) by the optimization of suppression of parasitic channels and device’s structure. |
|---|---|
| AbstractList | In this paper, the optimizations of vertically-stacked horizontal gate-all-around (GAA) Si nanosheet (NS) transistors on bulk Si substrate are systemically investigated. The release process of NS channels was firstly optimized to achieve uniform device structures. An over 100:1 selective wet-etch ratio of GeSi to Si layer was achieved for GeSi/Si stacks samples with different GeSi thickness (5 nm, 10 nm, and 20 nm) or annealing temperatures (≤900 °C). Furthermore, the influence of ground-plane (GP) doping in Si sub-fin region to improve electrical characteristics of devices was carefully investigated by experiment and simulations. The subthreshold characteristics of n-type devices were greatly improved with the increase of GP doping doses. However, the p-type devices initially were improved and then deteriorated with the increase of GP doping doses, and they demonstrated the best electrical characteristics with the GP doping concentrations of about 1 × 1018 cm−3, which was also confirmed by technical computer aided design (TCAD) simulation results. Finally, 4 stacked GAA Si NS channels with 6 nm in thickness and 30 nm in width were firstly fabricated on bulk substrate, and the performance of the stacked GAA Si NS devices achieved a larger ION/IOFF ratio (3.15 × 105) and smaller values of Subthreshold swings (SSs) (71.2 (N)/78.7 (P) mV/dec) and drain-induced barrier lowering (DIBLs) (9 (N)/22 (P) mV/V) by the optimization of suppression of parasitic channels and device’s structure. In this paper, the optimizations of vertically-stacked horizontal gate-all-around (GAA) Si nanosheet (NS) transistors on bulk Si substrate are systemically investigated. The release process of NS channels was firstly optimized to achieve uniform device structures. An over 100:1 selective wet-etch ratio of GeSi to Si layer was achieved for GeSi/Si stacks samples with different GeSi thickness (5 nm, 10 nm, and 20 nm) or annealing temperatures (≤900 °C). Furthermore, the influence of ground-plane (GP) doping in Si sub-fin region to improve electrical characteristics of devices was carefully investigated by experiment and simulations. The subthreshold characteristics of n-type devices were greatly improved with the increase of GP doping doses. However, the p-type devices initially were improved and then deteriorated with the increase of GP doping doses, and they demonstrated the best electrical characteristics with the GP doping concentrations of about 1 × 1018 cm-3, which was also confirmed by technical computer aided design (TCAD) simulation results. Finally, 4 stacked GAA Si NS channels with 6 nm in thickness and 30 nm in width were firstly fabricated on bulk substrate, and the performance of the stacked GAA Si NS devices achieved a larger ION/IOFF ratio (3.15 × 105) and smaller values of Subthreshold swings (SSs) (71.2 (N)/78.7 (P) mV/dec) and drain-induced barrier lowering (DIBLs) (9 (N)/22 (P) mV/V) by the optimization of suppression of parasitic channels and device's structure.In this paper, the optimizations of vertically-stacked horizontal gate-all-around (GAA) Si nanosheet (NS) transistors on bulk Si substrate are systemically investigated. The release process of NS channels was firstly optimized to achieve uniform device structures. An over 100:1 selective wet-etch ratio of GeSi to Si layer was achieved for GeSi/Si stacks samples with different GeSi thickness (5 nm, 10 nm, and 20 nm) or annealing temperatures (≤900 °C). Furthermore, the influence of ground-plane (GP) doping in Si sub-fin region to improve electrical characteristics of devices was carefully investigated by experiment and simulations. The subthreshold characteristics of n-type devices were greatly improved with the increase of GP doping doses. However, the p-type devices initially were improved and then deteriorated with the increase of GP doping doses, and they demonstrated the best electrical characteristics with the GP doping concentrations of about 1 × 1018 cm-3, which was also confirmed by technical computer aided design (TCAD) simulation results. Finally, 4 stacked GAA Si NS channels with 6 nm in thickness and 30 nm in width were firstly fabricated on bulk substrate, and the performance of the stacked GAA Si NS devices achieved a larger ION/IOFF ratio (3.15 × 105) and smaller values of Subthreshold swings (SSs) (71.2 (N)/78.7 (P) mV/dec) and drain-induced barrier lowering (DIBLs) (9 (N)/22 (P) mV/V) by the optimization of suppression of parasitic channels and device's structure. In this paper, the optimizations of vertically-stacked horizontal gate-all-around (GAA) Si nanosheet (NS) transistors on bulk Si substrate are systemically investigated. The release process of NS channels was firstly optimized to achieve uniform device structures. An over 100:1 selective wet-etch ratio of GeSi to Si layer was achieved for GeSi/Si stacks samples with different GeSi thickness (5 nm, 10 nm, and 20 nm) or annealing temperatures (≤900 °C). Furthermore, the influence of ground-plane (GP) doping in Si sub-fin region to improve electrical characteristics of devices was carefully investigated by experiment and simulations. The subthreshold characteristics of n -type devices were greatly improved with the increase of GP doping doses. However, the p -type devices initially were improved and then deteriorated with the increase of GP doping doses, and they demonstrated the best electrical characteristics with the GP doping concentrations of about 1 × 10 18 cm −3 , which was also confirmed by technical computer aided design (TCAD) simulation results. Finally, 4 stacked GAA Si NS channels with 6 nm in thickness and 30 nm in width were firstly fabricated on bulk substrate, and the performance of the stacked GAA Si NS devices achieved a larger I ON / I OFF ratio (3.15 × 10 5 ) and smaller values of Subthreshold swings ( SS s) (71.2 (N)/78.7 (P) mV/dec) and drain-induced barrier lowering ( DIBL s) (9 (N)/22 (P) mV/V) by the optimization of suppression of parasitic channels and device’s structure. In this paper, the optimizations of vertically-stacked horizontal gate-all-around (GAA) Si nanosheet (NS) transistors on bulk Si substrate are systemically investigated. The release process of NS channels was firstly optimized to achieve uniform device structures. An over 100:1 selective wet-etch ratio of GeSi to Si layer was achieved for GeSi/Si stacks samples with different GeSi thickness (5 nm, 10 nm, and 20 nm) or annealing temperatures (≤900 °C). Furthermore, the influence of ground-plane (GP) doping in Si sub-fin region to improve electrical characteristics of devices was carefully investigated by experiment and simulations. The subthreshold characteristics of -type devices were greatly improved with the increase of GP doping doses. However, the -type devices initially were improved and then deteriorated with the increase of GP doping doses, and they demonstrated the best electrical characteristics with the GP doping concentrations of about 1 × 10 cm , which was also confirmed by technical computer aided design (TCAD) simulation results. Finally, 4 stacked GAA Si NS channels with 6 nm in thickness and 30 nm in width were firstly fabricated on bulk substrate, and the performance of the stacked GAA Si NS devices achieved a larger / ratio (3.15 × 10 ) and smaller values of Subthreshold swings ( s) (71.2 (N)/78.7 (P) mV/dec) and drain-induced barrier lowering ( s) (9 (N)/22 (P) mV/V) by the optimization of suppression of parasitic channels and device's structure. |
| Author | Xu, Renren Yang, Hong Xu, Gaobo Radamson, Henry H. He, Xiaobin Zhang, Zhaohao Wang, Guilei Yao, Jiaxin Li, Junjie Luo, Jun Xiang, Jinjuan Wu, Zhenhua Zhang, Qingzhu Gu, Jie Cao, Lei Yin, Huaxiang Tian, Jiajia Kong, Zhenzhen Mao, Shujuan |
| AuthorAffiliation | 3 School of Microelectronics, University of Chinese Academy of Sciences, Beijing 100049, China 2 Key Laboratory of Microelectronics Devices and Integrated Technology, Institute of Microelectronics, CAS, Beijing 100029, China 1 Advanced Integrated Circuits R&D Center, Institute of Microelectronic of the Chinese Academy of Sciences, Beijing 100029, China; zhangqingzhu@ime.ac.cn (Q.Z.); gujie@ime.ac.cn (J.G.); xurenren@ime.ac.cn (R.X.); caolei@ime.ac.cn (L.C.); lijunjie@ime.ac.cn (J.L.); wuzhenhua@ime.ac.cn (Z.W.); wangguilei@ime.ac.cn (G.W.); yaojiaxin@ime.ac.cn (J.Y.); xiangjinjuan@ime.ac.cn (J.X.); hexiaobin@ime.ac.cn (X.H.); kongzhenzhen@ime.ac.cn (Z.K.); yanghong@ime.ac.cn (H.Y.); tianjiajia@ime.ac.cn (J.T.); xugaobo@ime.ac.cn (G.X.); maoshujuan@ime.ac.cn (S.M.); rad@ime.ac.cn (H.H.R.); luojun@ime.ac.cn (J.L.) |
| AuthorAffiliation_xml | – name: 3 School of Microelectronics, University of Chinese Academy of Sciences, Beijing 100049, China – name: 1 Advanced Integrated Circuits R&D Center, Institute of Microelectronic of the Chinese Academy of Sciences, Beijing 100029, China; zhangqingzhu@ime.ac.cn (Q.Z.); gujie@ime.ac.cn (J.G.); xurenren@ime.ac.cn (R.X.); caolei@ime.ac.cn (L.C.); lijunjie@ime.ac.cn (J.L.); wuzhenhua@ime.ac.cn (Z.W.); wangguilei@ime.ac.cn (G.W.); yaojiaxin@ime.ac.cn (J.Y.); xiangjinjuan@ime.ac.cn (J.X.); hexiaobin@ime.ac.cn (X.H.); kongzhenzhen@ime.ac.cn (Z.K.); yanghong@ime.ac.cn (H.Y.); tianjiajia@ime.ac.cn (J.T.); xugaobo@ime.ac.cn (G.X.); maoshujuan@ime.ac.cn (S.M.); rad@ime.ac.cn (H.H.R.); luojun@ime.ac.cn (J.L.) – name: 2 Key Laboratory of Microelectronics Devices and Integrated Technology, Institute of Microelectronics, CAS, Beijing 100029, China |
| Author_xml | – sequence: 1 givenname: Qingzhu orcidid: 0000-0003-0035-0652 surname: Zhang fullname: Zhang, Qingzhu – sequence: 2 givenname: Jie orcidid: 0000-0002-2043-1479 surname: Gu fullname: Gu, Jie – sequence: 3 givenname: Renren surname: Xu fullname: Xu, Renren – sequence: 4 givenname: Lei surname: Cao fullname: Cao, Lei – sequence: 5 givenname: Junjie orcidid: 0000-0001-5191-7992 surname: Li fullname: Li, Junjie – sequence: 6 givenname: Zhenhua orcidid: 0000-0003-4552-883X surname: Wu fullname: Wu, Zhenhua – sequence: 7 givenname: Guilei orcidid: 0000-0002-1311-8863 surname: Wang fullname: Wang, Guilei – sequence: 8 givenname: Jiaxin surname: Yao fullname: Yao, Jiaxin – sequence: 9 givenname: Zhaohao surname: Zhang fullname: Zhang, Zhaohao – sequence: 10 givenname: Jinjuan surname: Xiang fullname: Xiang, Jinjuan – sequence: 11 givenname: Xiaobin surname: He fullname: He, Xiaobin – sequence: 12 givenname: Zhenzhen orcidid: 0000-0001-8563-5424 surname: Kong fullname: Kong, Zhenzhen – sequence: 13 givenname: Hong orcidid: 0000-0003-2860-5901 surname: Yang fullname: Yang, Hong – sequence: 14 givenname: Jiajia surname: Tian fullname: Tian, Jiajia – sequence: 15 givenname: Gaobo orcidid: 0000-0002-4278-251X surname: Xu fullname: Xu, Gaobo – sequence: 16 givenname: Shujuan surname: Mao fullname: Mao, Shujuan – sequence: 17 givenname: Henry H. surname: Radamson fullname: Radamson, Henry H. – sequence: 18 givenname: Huaxiang orcidid: 0000-0001-8066-6002 surname: Yin fullname: Yin, Huaxiang – sequence: 19 givenname: Jun orcidid: 0000-0002-5122-6806 surname: Luo fullname: Luo, Jun |
| BackLink | https://www.ncbi.nlm.nih.gov/pubmed/33808024$$D View this record in MEDLINE/PubMed |
| BookMark | eNptkk9v1DAQxS1UREvpjTPykQMBx3YS-4JULf0nrehhgas1cSZdF2-82E6l7VfgS5PttmiL8MXW-L3fszXzmhwMYUBC3pbsoxCafRpgCGXJBKtl_YIccdboQmpdHuydD8lJSrdsWroUqhKvyKEQiinG5RH5fb3ObuXuIbsw0NDTRY6jzWNECkNHzzzaHJ0FT2dLiGAzRpeys4n2IdLzMMZiDhuM9AfGvNX5TbHIYH9iRy9DdPdhyJP5AjIWp94XpzGME3fh6Nfp6WmJmBP9gnfOYnpDXvbgE5487sfk-_nZt9llMb--uJqdzgsrK5YL3lbQNFxLZlnLZSVaJpoeRCc1qr4uWdcIxrCBCktrSwZC8F5hX6u2kbIV4phc7bhdgFuzjm4FcWMCOPNQCPHGwPYzHo3EtlbQ1U3VCsmVBJy4pWq4aJH3op5Yn3es9diusLM45Aj-GfT5zeCW5ibcmUZrJTWfAO8fATH8GjFls3LJovcwYBiT4RVTlWZcbbPe7Wf9DXnq5iTgO4GNIaWIvbEuP3R2inbelMxsp8bsT81k-vCP6Yn7X_kf1YvF4w |
| CitedBy_id | crossref_primary_10_1016_j_mejo_2025_106562 crossref_primary_10_1109_TED_2024_3469908 crossref_primary_10_1016_j_cej_2023_146257 crossref_primary_10_1149_2162_8777_ad8187 crossref_primary_10_3390_nano14100837 crossref_primary_10_1080_03772063_2024_2316322 crossref_primary_10_3390_nano13142127 crossref_primary_10_1186_s11671_024_04036_2 crossref_primary_10_2478_jee_2023_0058 crossref_primary_10_1109_LED_2024_3362986 crossref_primary_10_1109_TED_2023_3238376 crossref_primary_10_1149_2162_8777_adbebc crossref_primary_10_1149_2162_8777_ad670c crossref_primary_10_1109_LED_2024_3524259 crossref_primary_10_1007_s12633_022_01793_6 crossref_primary_10_1109_TVLSI_2025_3529504 crossref_primary_10_1186_s11671_022_03767_4 crossref_primary_10_1016_j_mejo_2024_106347 crossref_primary_10_1109_ACCESS_2024_3435691 crossref_primary_10_1109_JEDS_2025_3531432 crossref_primary_10_1109_LED_2023_3294545 crossref_primary_10_1007_s12598_024_02863_x crossref_primary_10_1109_TED_2022_3207972 crossref_primary_10_1093_nsr_nwae008 crossref_primary_10_1109_TED_2024_3358251 crossref_primary_10_1109_TNANO_2025_3546872 crossref_primary_10_3390_ma15196918 crossref_primary_10_1007_s12633_022_01989_w crossref_primary_10_1149_2162_8777_ac5d64 crossref_primary_10_1007_s12598_024_02674_0 crossref_primary_10_1007_s12633_022_01770_z crossref_primary_10_3390_nano13222971 crossref_primary_10_1116_6_0002222 crossref_primary_10_1149_2162_8777_ac0f12 crossref_primary_10_1109_LED_2024_3505926 crossref_primary_10_1109_TED_2022_3176843 crossref_primary_10_1109_TED_2023_3323449 crossref_primary_10_3390_nano13030504 crossref_primary_10_1109_TED_2023_3327968 crossref_primary_10_1016_j_mejo_2024_106535 crossref_primary_10_1109_TED_2022_3206179 crossref_primary_10_1049_ell2_70026 crossref_primary_10_1016_j_mejo_2023_105985 crossref_primary_10_1109_TNANO_2024_3447020 |
| Cites_doi | 10.1109/VLSIT.2014.6894390 10.1109/TED.2020.3017452 10.1109/TED.2020.2989416 10.1109/TED.2020.3007134 10.1109/LED.2017.2768484 10.1109/IEDM.2014.7046976 10.1109/IEDM.2018.8614629 10.1109/VLSITechnology18217.2020.9265025 10.3390/mi10050293 10.1109/VLSIT.2016.7573359 10.3390/nano10040793 10.23919/VLSIT.2017.7998183 10.1109/LED.2019.2891364 10.1109/IEDM19573.2019.8993490 10.1109/JEDS.2018.2858225 10.3390/nano10091715 10.1109/LED.2019.2954537 10.1109/LED.2018.2850366 10.1016/j.mssp.2020.105397 10.1016/j.sse.2016.12.016 10.1021/acs.nanolett.0c02950 10.1109/TED.2019.2912950 10.1149/2.0241811jss 10.1109/LED.2010.2080256 10.1109/IEDM.2016.7838456 10.1016/j.mssp.2020.105434 10.1021/acsami.0c14018 10.1016/j.mejo.2019.104679 10.1109/IEDM.2016.7838438 |
| ContentType | Journal Article |
| Copyright | 2021 by the authors. 2021 |
| Copyright_xml | – notice: 2021 by the authors. 2021 |
| DBID | AAYXX CITATION NPM 7X8 5PM DOA |
| DOI | 10.3390/nano11030646 |
| DatabaseName | CrossRef PubMed MEDLINE - Academic PubMed Central (Full Participant titles) DOAJ Directory of Open Access Journals |
| DatabaseTitle | CrossRef PubMed MEDLINE - Academic |
| DatabaseTitleList | CrossRef MEDLINE - Academic PubMed |
| Database_xml | – sequence: 1 dbid: DOA name: DOAJ Directory of Open Access Journals url: https://www.doaj.org/ sourceTypes: Open Website – sequence: 2 dbid: NPM name: PubMed url: https://proxy.k.utb.cz/login?url=http://www.ncbi.nlm.nih.gov/entrez/query.fcgi?db=PubMed sourceTypes: Index Database |
| DeliveryMethod | fulltext_linktorsrc |
| Discipline | Engineering |
| EISSN | 2079-4991 |
| ExternalDocumentID | oai_doaj_org_article_4eb68ad675b34284aee7a18723be2f36 PMC7998492 33808024 10_3390_nano11030646 |
| Genre | Journal Article |
| GrantInformation_xml | – fundername: the Science and technology program of Beijing Municipal Science and Technology Commission grantid: Z201100006820084 and Z201100004220001 – fundername: the National Key Project of Science and Technology of China grantid: 2017ZX02301007-001 and 2017ZX02315001-001 – fundername: the Youth Innovation Promotion Association, Chinese Academy of Sciences grantid: Y9YQ01R004 and Y2020037 – fundername: the Opening Project of Key Laboratory of Microelectronic Devices and Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences grantid: E0YS01X001 and E0290X03 – fundername: the National Natural Science Foundation of China grantid: 61904194 and 6187032253 |
| GroupedDBID | 53G 5VS 8FE 8FG 8FH AADQD AAFWJ AAHBH AAYXX ABJCF ADBBV ADMLS AENEX AFKRA AFPKN AFZYC ALMA_UNASSIGNED_HOLDINGS AOIJS BBNVY BCNDV BENPR BGLVJ BHPHI CCPQU CITATION D1I GROUPED_DOAJ HCIFZ HYE I-F IAO ITC KB. KQ8 LK8 M7P MODMG M~E OK1 PDBOC PGMZT PHGZM PHGZT PIMPY PROAC RPM NPM 7X8 PQGLB 5PM PUEGO |
| ID | FETCH-LOGICAL-c450t-2b5a772940c0b2453b037fa3d49e8f610d7300e7a5e1cc10a332f8ef68b744b33 |
| IEDL.DBID | DOA |
| ISSN | 2079-4991 |
| IngestDate | Wed Aug 27 01:32:08 EDT 2025 Thu Aug 21 13:38:45 EDT 2025 Thu Jul 10 19:29:12 EDT 2025 Wed Feb 19 02:28:00 EST 2025 Tue Jul 01 01:17:10 EDT 2025 Thu Apr 24 22:54:55 EDT 2025 |
| IsDoiOpenAccess | true |
| IsOpenAccess | true |
| IsPeerReviewed | true |
| IsScholarly | true |
| Issue | 3 |
| Keywords | channel release suppression nanosheet (NS) gate-all-around (GAA) parasitic channel |
| Language | English |
| License | https://creativecommons.org/licenses/by/4.0 Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/). |
| LinkModel | DirectLink |
| MergedId | FETCHMERGED-LOGICAL-c450t-2b5a772940c0b2453b037fa3d49e8f610d7300e7a5e1cc10a332f8ef68b744b33 |
| Notes | ObjectType-Article-1 SourceType-Scholarly Journals-1 ObjectType-Feature-2 content type line 23 |
| ORCID | 0000-0003-0035-0652 0000-0003-2860-5901 0000-0002-2043-1479 0000-0003-4552-883X 0000-0001-8563-5424 0000-0002-1311-8863 0000-0002-4278-251X 0000-0002-5122-6806 0000-0001-5191-7992 0000-0001-8066-6002 |
| OpenAccessLink | https://doaj.org/article/4eb68ad675b34284aee7a18723be2f36 |
| PMID | 33808024 |
| PQID | 2508590286 |
| PQPubID | 23479 |
| ParticipantIDs | doaj_primary_oai_doaj_org_article_4eb68ad675b34284aee7a18723be2f36 pubmedcentral_primary_oai_pubmedcentral_nih_gov_7998492 proquest_miscellaneous_2508590286 pubmed_primary_33808024 crossref_citationtrail_10_3390_nano11030646 crossref_primary_10_3390_nano11030646 |
| ProviderPackageCode | CITATION AAYXX |
| PublicationCentury | 2000 |
| PublicationDate | 20210305 |
| PublicationDateYYYYMMDD | 2021-03-05 |
| PublicationDate_xml | – month: 3 year: 2021 text: 20210305 day: 5 |
| PublicationDecade | 2020 |
| PublicationPlace | Switzerland |
| PublicationPlace_xml | – name: Switzerland |
| PublicationTitle | Nanomaterials (Basel, Switzerland) |
| PublicationTitleAlternate | Nanomaterials (Basel) |
| PublicationYear | 2021 |
| Publisher | MDPI MDPI AG |
| Publisher_xml | – name: MDPI – name: MDPI AG |
| References | Li (ref_9) 2017; 38 ref_14 ref_13 ref_11 Zhang (ref_25) 2021; 121 ref_30 Zhang (ref_18) 2018; 7 Sung (ref_26) 2020; 67 ref_17 Li (ref_19) 2020; 12 Yin (ref_7) 2019; 41 Huang (ref_10) 2019; 95 Song (ref_8) 2010; 31 Zhang (ref_15) 2019; 40 Hu (ref_24) 2020; 20 Kim (ref_27) 2020; 67 ref_22 Chu (ref_12) 2018; 39 ref_20 Su (ref_21) 2020; 67 Yao (ref_29) 2018; 6 ref_1 ref_3 Liu (ref_23) 2020; 121 ref_2 Shirazi (ref_6) 2019; 66 ref_28 Xu (ref_16) 2017; 129 ref_5 ref_4 |
| References_xml | – ident: ref_3 doi: 10.1109/VLSIT.2014.6894390 – volume: 67 start-page: 4085 year: 2020 ident: ref_21 article-title: Investigation of self-heating effects in vacuum gate dielectric gate-all-around vertically stacked silicon nanowire field effect transistors publication-title: IEEE Trans. Electron Devices doi: 10.1109/TED.2020.3017452 – volume: 67 start-page: 6 year: 2020 ident: ref_27 article-title: Investigation of electrical characteristic behavior induced by channel-release process in stacked nanosheet gate-all-around mosfets publication-title: IEEE Trans. Electron Devices doi: 10.1109/TED.2020.2989416 – ident: ref_28 – volume: 67 start-page: 9 year: 2020 ident: ref_26 article-title: Fabrication of vertically stacked nanosheet junctionless field-effect transistors and applications for the cmos and cfet inverters publication-title: IEEE Trans. Electron Devices doi: 10.1109/TED.2020.3007134 – volume: 38 start-page: 1653 year: 2017 ident: ref_9 article-title: Investigation on electrostatic discharge robustness of gate-all-around silicon nanowire transistors combined with thermal analysis publication-title: IEEE Electron Device Lett. doi: 10.1109/LED.2017.2768484 – ident: ref_1 doi: 10.1109/IEDM.2014.7046976 – ident: ref_11 doi: 10.1109/IEDM.2018.8614629 – ident: ref_14 doi: 10.1109/VLSITechnology18217.2020.9265025 – ident: ref_5 doi: 10.3390/mi10050293 – ident: ref_2 doi: 10.1109/VLSIT.2016.7573359 – ident: ref_20 doi: 10.3390/nano10040793 – ident: ref_30 doi: 10.23919/VLSIT.2017.7998183 – volume: 40 start-page: 367 year: 2019 ident: ref_15 article-title: Finfet with improved subthreshold swing and drain current using 3 nm ferroelectric hf0.5zr0.5o2 publication-title: IEEE Electron Device Lett. doi: 10.1109/LED.2019.2891364 – ident: ref_13 doi: 10.1109/IEDM19573.2019.8993490 – volume: 6 start-page: 841 year: 2018 ident: ref_29 article-title: Physical insights on quantum confinement and carrier mobility in si, sige, ge gate-all-around nsfet for 5nm technology node publication-title: IEEE J. Electron Devices Soc. doi: 10.1109/JEDS.2018.2858225 – ident: ref_22 doi: 10.3390/nano10091715 – volume: 41 start-page: 8 year: 2019 ident: ref_7 article-title: Vertical sandwich gate-all-around field-effect transistors with self-aligned high-k metal gates and small effective-gate-length variation publication-title: IEEE Electron Device Lett. doi: 10.1109/LED.2019.2954537 – volume: 39 start-page: 1133 year: 2018 ident: ref_12 article-title: Stacked ge-nanosheet gaa fets fabricated by ge/si multilayer epitaxy publication-title: IEEE Electron Device Lett. doi: 10.1109/LED.2018.2850366 – volume: 121 start-page: 105397 year: 2020 ident: ref_23 article-title: Fabrication and selective wet etching of si0.2ge0.8/ge multilayer for si0.2ge0.8 channel gate-all-around mosfets publication-title: Mater. Sci. Semicond. Process. doi: 10.1016/j.mssp.2020.105397 – volume: 129 start-page: 52 year: 2017 ident: ref_16 article-title: Two methods of tuning threshold voltage of bulk finfets with replacement high-k metal-gate stacks publication-title: Solid-State Electron. doi: 10.1016/j.sse.2016.12.016 – volume: 20 start-page: 10 year: 2020 ident: ref_24 article-title: Unprecedented uniform 3d growth integration of 10-layer stacked si nanowires on tightly confined sidewall grooves publication-title: Nano Lett. doi: 10.1021/acs.nanolett.0c02950 – volume: 66 start-page: 2822 year: 2019 ident: ref_6 article-title: GAA CNT TFETs Structural Engineering: A Higher ON Current, Lower Ambipolarity publication-title: IEEE Trans. Electron Devices doi: 10.1109/TED.2019.2912950 – volume: 7 start-page: 671 year: 2018 ident: ref_18 article-title: Influence of rapid thermal annealing on ge-si interdiffusion in epitaxial multilayer ge 0.3 si 0.7 /si superlattices with various gesi thicknesses publication-title: ECS J. Solid State Sci. Technol. doi: 10.1149/2.0241811jss – volume: 31 start-page: 1377 year: 2010 ident: ref_8 article-title: High-Performance Silicon Nanowire Gate-All-Around nMOSFETs Fabricated on BulkSubstrate Using CMOS-Compatible Process publication-title: IEEE Electron Device Lett. doi: 10.1109/LED.2010.2080256 – ident: ref_17 doi: 10.1109/IEDM.2016.7838456 – volume: 121 start-page: 105434 year: 2021 ident: ref_25 article-title: Optimization of zero-level interlayer dielectric materials for gate-all-around silicon nanowire channel fabrication in a replacement metal gate process publication-title: Mater. Sci. Semicond. Process. doi: 10.1016/j.mssp.2020.105434 – volume: 12 start-page: 48170 year: 2020 ident: ref_19 article-title: Selective Digital Etching of Silicon−Germanium Using Nitric and Hydrofluoric Acids publication-title: ACS Appl. Mater. Interfaces doi: 10.1021/acsami.0c14018 – volume: 95 start-page: 104679 year: 2019 ident: ref_10 article-title: Investigation and optimization of electrical and thermal performance for 5-nm gaa vertically stacked nanowire fets publication-title: Microelectron. J. doi: 10.1016/j.mejo.2019.104679 – ident: ref_4 doi: 10.1109/IEDM.2016.7838438 |
| SSID | ssj0000913853 |
| Score | 2.3715515 |
| Snippet | In this paper, the optimizations of vertically-stacked horizontal gate-all-around (GAA) Si nanosheet (NS) transistors on bulk Si substrate are systemically... |
| SourceID | doaj pubmedcentral proquest pubmed crossref |
| SourceType | Open Website Open Access Repository Aggregation Database Index Database Enrichment Source |
| StartPage | 646 |
| SubjectTerms | channel release gate-all-around (GAA) nanosheet (NS) parasitic channel suppression |
| Title | Optimization of Structure and Electrical Characteristics for Four-Layer Vertically-Stacked Horizontal Gate-All-Around Si Nanosheets Devices |
| URI | https://www.ncbi.nlm.nih.gov/pubmed/33808024 https://www.proquest.com/docview/2508590286 https://pubmed.ncbi.nlm.nih.gov/PMC7998492 https://doaj.org/article/4eb68ad675b34284aee7a18723be2f36 |
| Volume | 11 |
| hasFullText | 1 |
| inHoldings | 1 |
| isFullTextHit | |
| isPrint | |
| link | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwrV1Lj9MwELZgucAB8aY8KiPBCVmb-JE4x-7SUiG0IJZFe4tsZ6KtFBLUdg_wF_jTzDjZKkUgLlyTUWJ5Xt8k428Ye6lyaX0RCmGhUEJnPhOutjUxI_osuFxlIbJ9nmTLM_3u3JyPRn1RT1hPD9xv3KEGn1lXIa71CqGydgC5S20ulQdZq0i2jTlvVEzFGFykChNR3-musK4_bF3bpTRTKyOsO8pBkar_T_jy9zbJUd5Z3GG3B8DIZ_1C77Jr0N5jt0Y0gvfZzw_o91-HA5W8q_lpJIW9XAN3bcXncdINKYMf79Mzc0SsfIFvEO8dQm_-JTZZu6b5LhCEon9XfNmtVz86OjLJ6UObmDWNmK1pFhM_XXGMzd3mAmC74W8gxpwH7Gwx_3y8FMOQBRG0SbZCeuMIYeskJF5qo3yi8tqpShdgawRXFTHa454bSENIE6eUrC3UmfW51l6ph-yg7Vp4zDg-JxifBIMRVivpCwiuKqRBvYXUQjZhr6-2vQwDAzkNwmhKrERISeVYSRP2aif9rWfe-IvcEWlwJ0N82fECWlE5WFH5LyuasBdX-i_Rv-iniWuhu9yUCBFtpLhBmUe9PexeheU9HVXWE5bvWcreWvbvtKuLyOGdY5mrC_nkfyz-KbspqdOGOuPMM3aANgbPESpt_ZRdt4u3U3bjaH7y8dM0-sgv3icXnA |
| linkProvider | Directory of Open Access Journals |
| openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.atitle=Optimization+of+Structure+and+Electrical+Characteristics+for+Four-Layer+Vertically-Stacked+Horizontal+Gate-All-Around+Si+Nanosheets+Devices&rft.jtitle=Nanomaterials+%28Basel%2C+Switzerland%29&rft.au=Zhang%2C+Qingzhu&rft.au=Gu%2C+Jie&rft.au=Xu%2C+Renren&rft.au=Cao%2C+Lei&rft.date=2021-03-05&rft.issn=2079-4991&rft.eissn=2079-4991&rft.volume=11&rft.issue=3&rft_id=info:doi/10.3390%2Fnano11030646&rft_id=info%3Apmid%2F33808024&rft.externalDocID=33808024 |
| thumbnail_l | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/lc.gif&issn=2079-4991&client=summon |
| thumbnail_m | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/mc.gif&issn=2079-4991&client=summon |
| thumbnail_s | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/sc.gif&issn=2079-4991&client=summon |