1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS

• Published in: IEEE transactions on circuits and systems. II, Express briefs Vol. 53; no. 3; pp. 220 - 224
• Main Authors: Staszewski, R.B., Vemulapalli, S., Vallur, P., Wallberg, J., Balsara, P.T.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.03.2006; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: All digital; Calibration; Charge pumps; CMOS; Communication systems; compensation; Converters; deep-submicrometer CMOS; Detectors; Digital; Frequency conversion; frequency synthesizer; Frequency synthesizers; GSM; Inverters; MOS devices; MOSFETs; Phase detection; Phase frequency detector; Phase locked loops; Regenerative; time-to-digital converter (TDC); Transceivers
• ISSN: 1549-7747; 1558-3791
• DOI: 10.1109/TCSII.2005.858754

We propose and demonstrate a 20-ps time-to-digital converter (TDC) realized in 90-nm digital CMOS. It is used as a phase/frequency detector and charge pump replacement in an all-digital phase-locked loop for a fully-compliant Global System for Mobile Communications (GSM) transceiver. The TDC core is based on a pseudodifferential digital architecture that makes it insensitive to nMOS and pMOS transistor mismatches. The time conversion resolution is equal to an inverter propagation delay, which is the finest logic-level regenerative timing in CMOS. The TDC is self calibrating with the estimation accuracy better than 1%. It additionally serves as a CMOS process strength estimator for analog circuits in this large system-on-chip. Measured integral nonlinearity is 0.7 least significant bits. The TDC consumes 5.3 mA raw and 1.3 mA with power management from a 1.3-V supply.