Comparisons of Design and Yield for Large-Area 10-kV 4H-SiC DMOSFETs

Three large-area 10-kV 4H-SiC DMOSFET designs are compared with respect to their design, die area, breakdown yield, and ON-state yield. The largest of these DMOSFETs had 0.62 cm 2 of active area on a 1-cm 2 die, with a 10-kV device producing 40 A at a gate field of 3 MV/cm. Two designs used linear i...

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Published inIEEE transactions on electron devices Vol. 55; no. 8; pp. 1816 - 1823
Main Authors Howell, R.S., Buchoff, S., Van Campen, S., McNutt, T.R., Hearne, H., Ezis, A., Sherwin, M.E., Clarke, R.C., Singh, R.
Format Journal Article
LanguageEnglish
Published New York IEEE 01.08.2008
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects
Breakdown
Devices
Fingers
Gates
Photolithography
Power MOSFETs
power switching
silicon carbide
Wafers
yield optimization
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Summary:Three large-area 10-kV 4H-SiC DMOSFET designs are compared with respect to their design, die area, breakdown yield, and ON-state yield. The largest of these DMOSFETs had 0.62 cm 2 of active area on a 1-cm 2 die, with a 10-kV device producing 40 A at a gate field of 3 MV/cm. Two designs used linear interdigitated fingers, whereas the third design used a square cell layout. The linear interdigitated finger design proved to be more robust, with higher yields than the square cell geometry. It was determined that the square cell design was yield limited due to the impact of wafer bow and total thickness variations on photolithographic accuracy, making the square cell geometry less attractive for large-area 4H-SiC DMOSFETs.
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2008.926684