Performance and hot-carrier effects of small CRYO-CMOS devices

• Published in: IEEE transactions on electron devices Vol. 34; no. 1; pp. 8 - 18
• Main Authors: Aoki, M., Hanamura, S., Masuhara, T., Yano, K.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.01.1987; Institute of Electrical and Electronics Engineers
• Subjects: Applied sciences; Electronics; Exact sciences and technology; Integrated circuits; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Voltage threshold; VLSI circuit; Voltage current curve; Doping; Charge carrier mobility; Boron; Complementary MOS technology; Integrated circuit; Hot carrier; Semiconductivity; Silicon; Delay time; MOS transistor; Performance; Power; Transconductance; Low temperature
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/T-ED.1987.22880

The performance characteristics of submicrometer CMOS devices operating at low/cryogenic temperatures (CRYO-CMOS) are determined. The advantages and problems in a CRYO-CMOS technology are experimentally studied in relation to the velocity saturation, source-drain resistances, mobility behavior, carrier freeze-out effects, hot-carrier effects, and circuit performance. The increase of the maximum transconductance at low temperatures (77, 4.2 K) has been confirmed even in the submicrometer channel region. However, improvement of inabilities at a V G nearly equal to 5 V is not so significant in devices with thinner oxides and less so in pMOS devices than in nMOS devices. Excellent subthreshold characteristics have been obtained at low temperatures, making very low-voltage operation possible. One problem found in the threshold control of pMOS transistors is that the boron ions implanted in the surface freeze out, causing unusual subthreshold behavior. Circuit delays have been improved by a factor of 2 to 3, and CRYO-CMOS shows the lowest power-delay product among existing semiconductor technologies with speed performance comparable to bipolar ECL devices. For LDD devices, speed improvements are only slightly smaller than for single-drain devices, while currents and transconductances in the linear regions are limited because of carrier freeze-out of the lightly doped drain. For both channel LDD devices, the transconductance degradations and V T shifts observed under dc stress conditions at 77 K are considered to result from electron injection into spacer oxides.