Computational Study of the Ultimate Scaling Limits of CNT Tunneling Devices

• Published in: IEEE Transactions on Electron Devices Vol. 55; no. 1; pp. 313 - 321
• Main Authors: Poli, S., Reggiani, S., Gnudi, A., Gnani, E., Baccarani, G.
• Format: Book Review Journal Article
• Language: English
• Published: New York, NY IEEE 01.01.2008; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Band-to-band-tunneling (BTBT) devices; carbon nanotubes (CNTs); Computer simulation; Devices; Electronic equipment and fabrication. Passive components, printed wiring boards, connectics; Electronics; Exact sciences and technology; Gates; Logic gates; Mathematical model; Molecular electronics, nanoelectronics; MOSFETs; nonequilibrium Green's function (NEGF); Other multijunction devices. Power transistors. Thyristors; Oxides; Phonons; Power supplies; Scattering; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Semiconductors; transistor scaling; Transistors; Tunneling; Band-to-band-tunneling (BTBT) devices; nonequilibrium Green's function (NEGF); transistor scaling; carbon nanotubes (CNTs); MOSFET; Nanotube devices; Tunnel effect; Carbon nanotubes; n channel; Dual gate transistor; Power supply; Green function; Nanoelectronics; Power transistor; Field effect transistor; Inelastic scattering; Non equilibrium conditions; Numerical simulation; Phonon scattering; Low-power electronics; Effective mass; Tunneling device; Quantum transport
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2007.910563

The ultimate scaling limits of p-i-n carbon-nanotube field-effect transistors (CNT-FETs) are investigated through numerical simulations based on a quantum-mechanical transport within the nonequilibrium Green's function formalism, based on an energy-dependent effective mass, including inelastic phonon scattering. Starting from the projected specifications of the International Technology Roadmap for Semiconductors for the low-operating-power double-gate MOSFETs, the effect of variations of oxide thickness, power supply, and gate length has been systematically studied. The main conclusion is that there is no speed advantage in scaling the gate length of the p-i-n CNT-FETs below 16 nm due to the rapid increase of the tunneling current in the subthreshold region. A near optimum is found by keeping the gate length fixed at 16 nm and by scaling the oxide thickness and the power supply.