Power/Energy Minimization Techniques for Variability-Aware High-Performance 16-nm 6T-SRAM

• Published in: IEEE access Vol. 4; pp. 594 - 613
• Main Authors: Samandari-Rad, Jeren, Hughey, Richard
• Format: Journal Article
• Language: English
• Published: Piscataway IEEE 2016; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: 16-nm; 6T-SRAM; aging; Delay; Electromigration; Empirical analysis; Energy; Energy consumption; Energy efficiency; Energy management; energy-delay-product; IR drop; leakage current; Leakage currents; memory errors; Memory management; NBTI; Optimization; optimum architecture; power; Power system reliability; reliability; SRAM; Temperature; Temperature measurement; type of variations; variability; yield; IR drop; multi-threshold CMOS; Temperature; VLSI; high speed; type of variations; reliability; static random access memory; leakage current; 16-nm; electromigration; variability; NBTI; 6T-SRAM; energy-delay-product; memory errors; process variations; energy efficiency; yield; optimum architecture; low power; aging; RAM
• ISSN: 2169-3536; 2169-3536
• DOI: 10.1109/ACCESS.2016.2521385

Power and energy minimization is a critical concern for the battery life, reliability, and yield of many minimum-sized SRAMs. In this paper, we extend our previously proposed hybrid analytical-empirical model for minimizing and predicting the delay and delay variability of SRAMs, VAR-TX, to a new enhanced version, exVAR-TX, to minimize and predict the power/energy and power/energy variability of a 16-nm 6T-SRAM under the influence of the three major types of variations: Fabrication, Operation, and Implementation. Using exVAR-TX for architectural optimization [exhaustively computing and comparing the range of feasible architectures subject to interdie (die-to-die/D2D) and intradie (within-die/WID) process and operation variations (PVT), electromigration (EM), negative bias temperature instability (NBTI), and soft-errors, among others] on top of deploying the most recent state of the art effective mitigation techniques we show that energy and energy-delay-product (EDP) of 64KB 16-nm 6T-SRAM could be reduced by ~12.5X and ~33%, respectively, as compared to the existing conventional designs.