Delay Evaluation of Issue Queue in Superscalar Processors with Banking Tag RAM and Correct Critical Path Identification
This paper evaluates the delay of the issue queue in a superscalar processor to aid microarchitectural design, where quick quantification of the complexity of the issue queue is needed to consider the tradeoff between clock cycle time and instructions per cycle. Our study covers two aspects. First,...
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Published in | IEICE Transactions on Information and Systems Vol. E95.D; no. 9; pp. 2235 - 2246 |
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Main Authors | , , |
Format | Journal Article |
Language | English |
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Oxford
The Institute of Electronics, Information and Communication Engineers
2012
Oxford University Press |
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Abstract | This paper evaluates the delay of the issue queue in a superscalar processor to aid microarchitectural design, where quick quantification of the complexity of the issue queue is needed to consider the tradeoff between clock cycle time and instructions per cycle. Our study covers two aspects. First, we introduce banking tag RAM, which comprises the issue queue, to reduce the delay. Unlike normal RAM, this is not straightforward, because of the uniqueness of the issue queue organization. Second, we explore and identify the correct critical path in the issue queue. In a previous study, the critical path of each component in the issue queue was summed to obtain the issue queue delay, but this does not give the correct delay of the issue queue, because the critical paths of the components are not connected logically. In the evaluation assuming 32-nm LSI technology, we obtained the delays of issue queues with eight to 128 entries. The process of banking tag RAM and identifying the correct critical path reduces the delay by up to 20% and 23% for 4- and 8-issue widths, respectively, compared with not banking tag RAM and simply summing the critical path delay of each component. |
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AbstractList | This paper evaluates the delay of the issue queue in a superscalar processor to aid microarchitectural design, where quick quantification of the complexity of the issue queue is needed to consider the tradeoff between clock cycle time and instructions per cycle. Our study covers two aspects. First, we introduce banking tag RAM, which comprises the issue queue, to reduce the delay. Unlike normal RAM, this is not straightforward, because of the uniqueness of the issue queue organization. Second, we explore and identify the correct critical path in the issue queue. In a previous study, the critical path of each component in the issue queue was summed to obtain the issue queue delay, but this does not give the correct delay of the issue queue, because the critical paths of the components are not connected logically. In the evaluation assuming 32-nm LSI technology, we obtained the delays of issue queues with eight to 128 entries. The process of banking tag RAM and identifying the correct critical path reduces the delay by up to 20% and 23% for 4- and 8-issue widths, respectively, compared with not banking tag RAM and simply summing the critical path delay of each component. |
Author | ANDO, Hideki KORA, Yuya YAMAGUCHI, Kyohei |
Author_xml | – sequence: 1 fullname: YAMAGUCHI, Kyohei organization: Department of Electrical Engineering and Computer Science, Nagoya University – sequence: 2 fullname: KORA, Yuya organization: Department of Computational Science and Engineering, Nagoya University – sequence: 3 fullname: ANDO, Hideki organization: Department of Electrical Engineering and Computer Science, Nagoya University |
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Cites_doi | 10.1145/384286.264201 10.1109/40.755465 10.1111/j.1545-5300.1998.00167.x 10.1145/264107.264201 10.1145/1250662.1250704 10.1109/40.491460 10.1109/ICCD.2011.6081417 |
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Copyright | 2012 The Institute of Electronics, Information and Communication Engineers 2015 INIST-CNRS |
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Keywords | LSI circuit Random access memory Superscalar processor Clock delay complexity Non volatile memory Integrated circuit issue queue Critical path Delay time Microprocessor Queue Execution time |
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Snippet | This paper evaluates the delay of the issue queue in a superscalar processor to aid microarchitectural design, where quick quantification of the complexity of... |
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SubjectTerms | Applied sciences complexity delay Design. Technologies. Operation analysis. Testing Electronics Exact sciences and technology Integrated circuits Integrated circuits by function (including memories and processors) issue queue microprocessor Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices superscalar processor |
Title | Delay Evaluation of Issue Queue in Superscalar Processors with Banking Tag RAM and Correct Critical Path Identification |
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