Design and test methodology for an analog-to-digital converter multichip module for experimental all-digital radar receiver operating at 2 gigasamples/s
In this paper, we describe the development of an analog-to-digital (A/D) converter subsystem, based on a monolithic A/D converter chip, a demultiplexer chip, and a laminate multichip module, for an experimental all-digital receiver for an airborne radar. The evolution of techniques for recording and...
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Published in | IEEE transactions on advanced packaging Vol. 22; no. 4; pp. 649 - 664 |
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Main Authors | , , , , , |
Format | Journal Article Conference Proceeding |
Language | English |
Published |
Piscataway, NY
IEEE
01.11.1999
Institute of Electrical and Electronics Engineers |
Subjects | |
Online Access | Get full text |
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Summary: | In this paper, we describe the development of an analog-to-digital (A/D) converter subsystem, based on a monolithic A/D converter chip, a demultiplexer chip, and a laminate multichip module, for an experimental all-digital receiver for an airborne radar. The evolution of techniques for recording and analyzing all the data from the assembled multichip module at the full sample rate of the A/D converter, and the ways in which this test data can be used to analyze the performance of A/D converters, are described. The problems which arise in the testing of GHz A/D converters, a number of which are unique to A/D conversion at such high sample rates, are pointed out. Finally, comments on future directions in the test of high performance A/D converters are presented. |
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Bibliography: | ObjectType-Article-2 SourceType-Scholarly Journals-1 ObjectType-Feature-1 content type line 23 |
ISSN: | 1521-3323 1557-9980 |
DOI: | 10.1109/6040.803458 |