A self‐biased and all‐in‐one voltage and current reference
This Letter presents a high‐performance self‐biased and all‐in‐one voltage and current reference without BJT and V–I converter exploiting the zero‐temperature‐coefficient point of the N‐type MOSFET. With the help of the low‐temperature‐coefficient resistors and the self‐biased two‐stage OTA structur...
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Published in | Electronics letters Vol. 57; no. 1; pp. 6 - 8 |
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Main Authors | , , , , |
Format | Journal Article |
Language | English |
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John Wiley & Sons, Inc
01.01.2021
Wiley |
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Abstract | This Letter presents a high‐performance self‐biased and all‐in‐one voltage and current reference without BJT and V–I converter exploiting the zero‐temperature‐coefficient point of the N‐type MOSFET. With the help of the low‐temperature‐coefficient resistors and the self‐biased two‐stage OTA structure, the all‐in‐one reference can achieve the average temperature coefficients of 6.6 and 34 ppm/°C of voltage and current reference from −40 to 125 °C, respectively. Meanwhile, the line sensitivities are 0.08%/V and 0.23%/V of voltage and current reference. And the power supply rejection ratio of the voltage reference is −93 dB@100 Hz with the power consumption of 12.6 μW@tt corner and VDD = 2.5 V. The reference circuit is realized in a standard 180 nm CMOS process with the area of 0.0621 mm × mm. |
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AbstractList | This Letter presents a high‐performance self‐biased and all‐in‐one voltage and current reference without BJT and V–I converter exploiting the zero‐temperature‐coefficient point of the N‐type MOSFET. With the help of the low‐temperature‐coefficient resistors and the self‐biased two‐stage OTA structure, the all‐in‐one reference can achieve the average temperature coefficients of 6.6 and 34 ppm/°C of voltage and current reference from −40 to 125 °C, respectively. Meanwhile, the line sensitivities are 0.08%/V and 0.23%/V of voltage and current reference. And the power supply rejection ratio of the voltage reference is −93 dB@100 Hz with the power consumption of 12.6 μW@tt corner and VDD = 2.5 V. The reference circuit is realized in a standard 180 nm CMOS process with the area of 0.0621 mm × mm. This Letter presents a high‐performance self‐biased and all‐in‐one voltage and current reference without BJT and V–I converter exploiting the zero‐temperature‐coefficient point of the N‐type MOSFET. With the help of the low‐temperature‐coefficient resistors and the self‐biased two‐stage OTA structure, the all‐in‐one reference can achieve the average temperature coefficients of 6.6 and 34 ppm/°C of voltage and current reference from −40 to 125 °C, respectively. Meanwhile, the line sensitivities are 0.08%/V and 0.23%/V of voltage and current reference. And the power supply rejection ratio of the voltage reference is −93 dB@100 Hz with the power consumption of 12.6 μW@tt corner and VDD = 2.5 V. The reference circuit is realized in a standard 180 nm CMOS process with the area of 0.0621 mm × mm. Abstract This Letter presents a high‐performance self‐biased and all‐in‐one voltage and current reference without BJT and V–I converter exploiting the zero‐temperature‐coefficient point of the N‐type MOSFET. With the help of the low‐temperature‐coefficient resistors and the self‐biased two‐stage OTA structure, the all‐in‐one reference can achieve the average temperature coefficients of 6.6 and 34 ppm/°C of voltage and current reference from −40 to 125 °C, respectively. Meanwhile, the line sensitivities are 0.08%/V and 0.23%/V of voltage and current reference. And the power supply rejection ratio of the voltage reference is −93 dB@100 Hz with the power consumption of 12.6 μW@tt corner and VDD = 2.5 V. The reference circuit is realized in a standard 180 nm CMOS process with the area of 0.0621 mm × mm. |
Author | Luo, Ping Yang, Bingzhong Tang, Tianyuan Wang, Yuanfei Zhang, Bo |
Author_xml | – sequence: 1 givenname: Yuanfei orcidid: 0000-0003-2247-0997 surname: Wang fullname: Wang, Yuanfei organization: University of Electronic Science and Technology of China – sequence: 2 givenname: Ping surname: Luo fullname: Luo, Ping email: pingl@uestc.edu.cn organization: University of Electronic Science and Technology of China – sequence: 3 givenname: Bingzhong surname: Yang fullname: Yang, Bingzhong organization: University of Electronic Science and Technology of China – sequence: 4 givenname: Tianyuan surname: Tang fullname: Tang, Tianyuan organization: University of Electronic Science and Technology of China – sequence: 5 givenname: Bo surname: Zhang fullname: Zhang, Bo organization: University of Electronic Science and Technology of China |
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Copyright | 2020 The Authors. published by John Wiley & Sons Ltd on behalf of The Institution of Engineering and Technology 2021. This work is published under http://creativecommons.org/licenses/by/4.0/ (the "License"). Notwithstanding the ProQuest Terms and Conditions, you may use this content in accordance with the terms of the License. |
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Snippet | This Letter presents a high‐performance self‐biased and all‐in‐one voltage and current reference without BJT and V–I converter exploiting the... Abstract This Letter presents a high‐performance self‐biased and all‐in‐one voltage and current reference without BJT and V–I converter exploiting the... |
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SubjectTerms | Circuits CMOS integrated circuits Design Electric potential Power electronics, supply and supervisory circuits Power supply Temperature effects Voltage |
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Title | A self‐biased and all‐in‐one voltage and current reference |
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