A Monolithically-Integrated Optical Receiver in Standard 45-nm SOI

• Published in: IEEE journal of solid-state circuits Vol. 47; no. 7; pp. 1693 - 1702
• Main Authors: Georgas, M., Orcutt, J., Ram, R. J., Stojanovic, V.
• Format: Journal Article Conference Proceeding
• Language: English
• Published: New York, NY IEEE 01.07.2012; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Bandwidth; Capacitance; chip-to-chip links; Circuit properties; Circuits; Clocks; Design. Technologies. Operation analysis. Testing; Electric, optical and optoelectronic circuits; Electronics; Exact sciences and technology; Hardware; high-speed I/O; Input-output equipment; Integrated circuits; Integrated circuits by function (including memories and processors); Integrated optics. Optical fibers and wave guides; integrating receivers; interconnect; many-core; monolithic integration; multi-core; Optical and optoelectronic circuits; Optical receivers; Optical sensors; Photodiodes; Photonics; Power consumption; Receivers; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; sense-amplifiers; Sensitivity; SOI; transimpedance amplifiers; Integrated optics; multi-core; sense-amplifiers; Processor; In situ; monolithic integration; many-core; Clock; Photonics; Wiring; Silicon on insulator technology; User interface; Energetic efficiency; High sensitivity; Transimpedance; Optoelectronic device; Electric power consumption; Optical receiver; transimpedance amplifiers; Comparator circuit; Monolithic integrated circuit; integrating receivers; Operational amplifier; high-speed I/O; chip-to-chip links; Photodiode; SOI; interconnect; Sense amplifier; Interconnection; Integrated circuit; Capacitance
• DOI: 10.1109/JSSC.2012.2191684
• ISSN: 0018-9200

Integrated photonics has emerged as an I/O technology that can meet the throughput demands of future many-core processors. Taking advantage of the low capacitance environment provided by monolithic integration, we developed an integrating receiver front-end built directly into a clocked comparator, achieving high sensitivity and energy-efficiency. A simple model of the receiver provides intuition on the effects of wiring and photodiode capacitance, and leads to a photodiode-splitting technique enabling improved sensitivity at higher data rates. The receiver is characterized in situ and shown to operate with μA-sensitivity at 3.5 Gb/s with a power consumption of 180 μ W (52 fJ/bit) and area of 108 μm 2 . This work demonstrates that photonics and electronics can be jointly integrated in a standard 45-nm SOI process.