Digital Implementation of a Single Dynamical Node Reservoir Computer

• Published in: IEEE transactions on circuits and systems. II, Express briefs Vol. 62; no. 10; pp. 977 - 981
• Main Authors: Alomar, Miquel L., Soriano, Miguel C., Escalona-Morán, Miguel, Canals, Vincent, Fischer, Ingo, Mirasso, Claudio R., Rosselló, Jose L.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.10.2015; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Artificial Neural Networks (ANN); Circuits; Classification; Computers; Delays; Digital computers; Dynamical systems; Dynamics; Field programmable gate arrays; field-programmable gate arrays (FPGA); Hardware; hardware (HW); multiple signal classification; neural network (NN); Neural networks; pattern recognition; Random access memory; recurrent neural networks (RNN); Reservoirs; time series prediction; Training; recurrent neural networks (RNN); hardware (HW); multiple signal classification; field-programmable gate arrays (FPGAs); time-series prediction; neural network (NN); Artificial neural networks (ANNs); pattern recognition
• ISSN: 1549-7747; 1558-3791
• DOI: 10.1109/TCSII.2015.2458071

Minimal hardware implementations of machine-learning techniques have been attracting increasing interest over the last decades. In particular, field-programmable gate array (FPGA) implementations of neural networks (NNs) are among the most appealing ones, given the match between system requirements...