Optimal IP Assignment for Efficient NoC-based System Implementation using NSGA-II and MicroGA
Network-on-chip (NoC) are considered the next generation of communication infrastructure, which will be omnipresent in most of industry, office and personal electronic systems. In platform-based methodology, an application is implemented by a set of collaborating intellectual properties (IPs) blocks...
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Published in | International journal of computational intelligence systems Vol. 2; no. 2; pp. 115 - 123 |
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Main Authors | , , |
Format | Journal Article |
Language | English |
Published |
Dordrecht
Springer Netherlands
01.06.2009
Springer |
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Abstract | Network-on-chip (NoC) are considered the next generation of communication infrastructure, which will be omnipresent in most of industry, office and personal electronic systems. In platform-based methodology, an application is implemented by a set of collaborating intellectual properties (IPs) blocks. In this paper, we use two multi-objective evolutionary algorithms to address the problem of selecting the most adequate set of IPs (from an available library) that best implements the application. The IP selection optimization is driven by the minimization of hardware area, total execution time and power consumption. |
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AbstractList | Network-on-chip (NoC) are considered the next generation of communication infrastructure, which will be omnipresent in most of industry, office and personal electronic systems. In platform-based methodology, an application is implemented by a set of collaborating intellectual properties (IPs) blocks. In this paper, we use two multi-objective evolutionary algorithms to address the problem of selecting the most adequate set of IPs (from an available library) that best implements the application. The IP selection optimization is driven by the minimization of hardware area, total execution time and power consumption. |
Author | Mourelle, Luiza de Macedo da Silva, Marcus Vinícius Carvalho Nedjah, Nadia |
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Title | Optimal IP Assignment for Efficient NoC-based System Implementation using NSGA-II and MicroGA |
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