60-GHz Four-Element Phased-Array Transmit/Receive System-in-Package Using Phase Compensation Techniques in 65-nm Flip-Chip CMOS Process
AThe 60-GHz four-element phased-array transmit/receive (TX/RX) system-in-package antenna modules with phase-compensated techniques in 65-nm CMOS technology are presented. The design is based on the all-RF architecture with 4-bit RF switched LC phase shifters, phase compensated variable gain amplifie...
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Published in | IEEE transactions on microwave theory and techniques Vol. 60; no. 3; pp. 743 - 756 |
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Main Authors | , , , , , , , , , , , , , , , , , , |
Format | Journal Article |
Language | English |
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New York
IEEE
01.03.2012
The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
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Abstract | AThe 60-GHz four-element phased-array transmit/receive (TX/RX) system-in-package antenna modules with phase-compensated techniques in 65-nm CMOS technology are presented. The design is based on the all-RF architecture with 4-bit RF switched LC phase shifters, phase compensated variable gain amplifier (VGA), 4:1 Wilkinson power combining/dividing network, variable-gain low-noise amplifier, power amplifier, 6-bit unary digital-to-analog converter, bias circuit, electrostatic discharge protection, and digital control interface (DCI). The 2 × 2 TX/RX phased arrays have been packaged with four antennas in low-temperature co-fired ceramic modules through flip-chip bonding and underfill process, and phased-array beam steering have been demonstrated. The entire beam-steering functions are digitally controllable, and individual registers are integrated at each front-end to enable beam steering through the DCI. The four-element TX array results in an output of 5 dBm per channel. The four-element RX array results in an average gain of 25 dB per channel. The four-element array consumes 400 mW in TX and 180 mW in RX and occupies an area of 3.74 mm 2 in the TX integrated circuit (IC) and 4.18 mm 2 in the RX IC. The beam-steering measurement results show acceptable agreement of the synthesized and measured array pattern. |
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AbstractList | AThe 60-GHz four-element phased-array transmit/receive (TX/RX) system-in-package antenna modules with phase-compensated techniques in 65-nm CMOS technology are presented. The design is based on the all-RF architecture with 4-bit RF switched LC phase shifters, phase compensated variable gain amplifier (VGA), 4:1 Wilkinson power combining/dividing network, variable-gain low-noise amplifier, power amplifier, 6-bit unary digital-to-analog converter, bias circuit, electrostatic discharge protection, and digital control interface (DCI). The 2 × 2 TX/RX phased arrays have been packaged with four antennas in low-temperature co-fired ceramic modules through flip-chip bonding and underfill process, and phased-array beam steering have been demonstrated. The entire beam-steering functions are digitally controllable, and individual registers are integrated at each front-end to enable beam steering through the DCI. The four-element TX array results in an output of 5 dBm per channel. The four-element RX array results in an average gain of 25 dB per channel. The four-element array consumes 400 mW in TX and 180 mW in RX and occupies an area of 3.74 mm 2 in the TX integrated circuit (IC) and 4.18 mm 2 in the RX IC. The beam-steering measurement results show acceptable agreement of the synthesized and measured array pattern. AThe 60-GHz four-element phased-array transmit/receive (TX/RX) system-in-package antenna modules with phase-compensated techniques in 65-nm CMOS technology are presented. The design is based on the all-RF architecture with 4-bit RF switched LC phase shifters, phase compensated variable gain amplifier (VGA), 4:1 Wilkinson power combining/dividing network, variable-gain low-noise amplifier, power amplifier, 6-bit unary digital-to-analog converter, bias circuit, electrostatic discharge protection, and digital control interface (DCI). The 2 2 TX/RX phased arrays have been packaged with four antennas in low-temperature co-fired ceramic modules through flip-chip bonding and underfill process, and phased-array beam steering have been demonstrated. The entire beam-steering functions are digitally controllable, and individual registers are integrated at each front-end to enable beam steering through the DCI. The four-element TX array results in an output P rm 1 dB of 5 dBm per channel. The four-element RX array results in an average gain of 25 dB per channel. The four-element array consumes 400 mW in TX and 180 mW in RX and occupies an area of 3.74 mm 2 in the TX integrated circuit (IC) and 4.18 mm 2 in the RX IC. The beam-steering measurement results show acceptable agreement of the synthesized and measured array pattern. AThe 60-GHz four-element phased-array transmit/receive (TX/RX) system-in-package antenna modules with phase-compensated techniques in 65-nm CMOS technology are presented. The design is based on the all-RF architecture with 4-bit RF switched LC phase shifters, phase compensated variable gain amplifier (VGA), 4:1 Wilkinson power combining/dividing network, variable-gain low-noise amplifier, power amplifier, 6-bit unary digital-to-analog converter, bias circuit, electrostatic discharge protection, and digital control interface (DCI). The 2[Formula Omitted]2 TX/RX phased arrays have been packaged with four antennas in low-temperature co-fired ceramic modules through flip-chip bonding and underfill process, and phased-array beam steering have been demonstrated. The entire beam-steering functions are digitally controllable, and individual registers are integrated at each front-end to enable beam steering through the DCI. The four-element TX array results in an output [Formula Omitted] of 5 dBm per channel. The four-element RX array results in an average gain of 25 dB per channel. The four-element array consumes 400 mW in TX and 180 mW in RX and occupies an area of 3.74 mm[Formula Omitted] in the TX integrated circuit (IC) and 4.18 mm[Formula Omitted] in the RX IC. The beam-steering measurement results show acceptable agreement of the synthesized and measured array pattern. |
Author | Yi-Fong Lu Wei-Yuan Hsiung Hsu, Y. A. Huei Wang Kun-You Lin Ruey-Beei Wu Liang-Hung Lu Wang, J. Yi-Cheng Lin Tian-Wei Huang Ting-Yi Huang Hsin-Chia Lu Jing-Lin Kuo Yi-Long Chang Tzung-Chuen Tsai Yi-Keng Hsieh I-Chih Chang Kun-Yao Kao Pen-Jui Peng |
Author_xml | – sequence: 1 surname: Jing-Lin Kuo fullname: Jing-Lin Kuo organization: Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan – sequence: 2 surname: Yi-Fong Lu fullname: Yi-Fong Lu organization: Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan – sequence: 3 surname: Ting-Yi Huang fullname: Ting-Yi Huang organization: Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan – sequence: 4 surname: Yi-Long Chang fullname: Yi-Long Chang organization: Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan – sequence: 5 surname: Yi-Keng Hsieh fullname: Yi-Keng Hsieh organization: Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan – sequence: 6 surname: Pen-Jui Peng fullname: Pen-Jui Peng organization: Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan – sequence: 7 surname: I-Chih Chang fullname: I-Chih Chang organization: Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan – sequence: 8 surname: Tzung-Chuen Tsai fullname: Tzung-Chuen Tsai organization: Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan – sequence: 9 surname: Kun-Yao Kao fullname: Kun-Yao Kao organization: Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan – sequence: 10 surname: Wei-Yuan Hsiung fullname: Wei-Yuan Hsiung organization: Wireless Local Area Network Div., MediaTek Inc., Hsinchu, Taiwan – sequence: 11 givenname: J. surname: Wang fullname: Wang, J. organization: Wireless Local Area Network Div., MediaTek Inc., Hsinchu, Taiwan – sequence: 12 givenname: Y. A. surname: Hsu fullname: Hsu, Y. A. organization: Wireless Local Area Network Div., MediaTek Inc., Hsinchu, Taiwan – sequence: 13 surname: Kun-You Lin fullname: Kun-You Lin organization: Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan – sequence: 14 surname: Hsin-Chia Lu fullname: Hsin-Chia Lu organization: Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan – sequence: 15 surname: Yi-Cheng Lin fullname: Yi-Cheng Lin organization: Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan – sequence: 16 surname: Liang-Hung Lu fullname: Liang-Hung Lu organization: Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan – sequence: 17 surname: Tian-Wei Huang fullname: Tian-Wei Huang organization: Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan – sequence: 18 surname: Ruey-Beei Wu fullname: Ruey-Beei Wu organization: Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan – sequence: 19 surname: Huei Wang fullname: Huei Wang email: hueiwang@ntu.edu.tw organization: Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan |
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SubjectTerms | 60 GHz Amplifiers Antennas Arrays Beam steering Beamforming Channels CMOS Digital control flip-chip Gain Integrated circuits Modules Noise levels Phase shifters phase-compensated techniques phased array Phased arrays Power dividers Semiconductors Switches system-in-package (SiP) Transmitters variable gain amplifier (VGA) wireless communication |
Title | 60-GHz Four-Element Phased-Array Transmit/Receive System-in-Package Using Phase Compensation Techniques in 65-nm Flip-Chip CMOS Process |
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